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ARM Encoding information for UXTAH and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119753 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -752,7 +752,14 @@ multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
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IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
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IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
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[(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
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[(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
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Requires<[IsARM, HasV6]> {
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Requires<[IsARM, HasV6]> {
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bits<4> Rd;
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bits<4> Rm;
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bits<4> Rn;
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let Inst{19-16} = Rn;
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let Inst{15-12} = Rd;
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let Inst{11-10} = 0b00;
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let Inst{11-10} = 0b00;
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let Inst{9-4} = 0b000111;
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let Inst{3-0} = Rm;
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}
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}
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def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
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def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
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rot_imm:$rot),
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rot_imm:$rot),
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@ -760,10 +767,15 @@ multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
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[(set GPR:$Rd, (opnode GPR:$Rn,
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[(set GPR:$Rd, (opnode GPR:$Rn,
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(rotr GPR:$Rm, rot_imm:$rot)))]>,
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(rotr GPR:$Rm, rot_imm:$rot)))]>,
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Requires<[IsARM, HasV6]> {
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Requires<[IsARM, HasV6]> {
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bits<4> Rd;
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bits<4> Rm;
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bits<4> Rn;
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bits<4> Rn;
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bits<2> rot;
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bits<2> rot;
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let Inst{19-16} = Rn;
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let Inst{19-16} = Rn;
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let Inst{15-12} = Rd;
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let Inst{11-10} = rot;
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let Inst{11-10} = rot;
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let Inst{9-4} = 0b000111;
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let Inst{3-0} = Rm;
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}
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}
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}
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}
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