mirror of
https://github.com/c64scene-ar/llvm-6502.git
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[Sparc] Add support for soft long double (fp128).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189780 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Venkatraman Govindaraju
parent
4ccfbedaed
commit
75ddb2bb34
@ -915,6 +915,22 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
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return Chain;
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}
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// This functions returns true if CalleeName is a ABI function that returns
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// a long double (fp128).
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static bool isFP128ABICall(const char *CalleeName)
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{
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static const char *const ABICalls[] =
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{ "_Q_add", "_Q_sub", "_Q_mul", "_Q_div",
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"_Q_sqrt", "_Q_neg",
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"_Q_itoq", "_Q_stoq", "_Q_dtoq", "_Q_utoq",
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0
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};
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for (const char * const *I = ABICalls; I != 0; ++I)
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if (strcmp(CalleeName, *I) == 0)
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return true;
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return false;
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}
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unsigned
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SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const
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{
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@ -925,7 +941,10 @@ SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const
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dyn_cast<ExternalSymbolSDNode>(Callee)) {
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const Function *Fn = DAG.getMachineFunction().getFunction();
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const Module *M = Fn->getParent();
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CalleeFn = M->getFunction(E->getSymbol());
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const char *CalleeName = E->getSymbol();
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CalleeFn = M->getFunction(CalleeName);
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if (!CalleeFn && isFP128ABICall(CalleeName))
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return 16; // Return sizeof(fp128)
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}
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if (!CalleeFn)
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@ -1428,6 +1447,47 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::FNEG, MVT::f128, Custom);
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setOperationAction(ISD::FABS, MVT::f128, Custom);
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}
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} else {
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// Custom legalize f128 operations.
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setOperationAction(ISD::FADD, MVT::f128, Custom);
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setOperationAction(ISD::FSUB, MVT::f128, Custom);
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setOperationAction(ISD::FMUL, MVT::f128, Custom);
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setOperationAction(ISD::FDIV, MVT::f128, Custom);
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setOperationAction(ISD::FSQRT, MVT::f128, Custom);
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setOperationAction(ISD::FNEG, MVT::f128, Custom);
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setOperationAction(ISD::FABS, MVT::f128, Custom);
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setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
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setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
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setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
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// Setup Runtime library names.
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if (Subtarget->is64Bit()) {
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setLibcallName(RTLIB::ADD_F128, "_Qp_add");
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setLibcallName(RTLIB::SUB_F128, "_Qp_sub");
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setLibcallName(RTLIB::MUL_F128, "_Qp_mul");
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setLibcallName(RTLIB::DIV_F128, "_Qp_div");
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setLibcallName(RTLIB::SQRT_F128, "_Qp_sqrt");
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setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Qp_qtoi");
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setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Qp_itoq");
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setLibcallName(RTLIB::FPEXT_F32_F128, "_Qp_stoq");
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setLibcallName(RTLIB::FPEXT_F64_F128, "_Qp_dtoq");
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setLibcallName(RTLIB::FPROUND_F128_F32, "_Qp_qtos");
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setLibcallName(RTLIB::FPROUND_F128_F64, "_Qp_qtod");
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} else {
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setLibcallName(RTLIB::ADD_F128, "_Q_add");
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setLibcallName(RTLIB::SUB_F128, "_Q_sub");
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setLibcallName(RTLIB::MUL_F128, "_Q_mul");
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setLibcallName(RTLIB::DIV_F128, "_Q_div");
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setLibcallName(RTLIB::SQRT_F128, "_Q_sqrt");
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setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Q_qtoi");
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setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Q_itoq");
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setLibcallName(RTLIB::FPEXT_F32_F128, "_Q_stoq");
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setLibcallName(RTLIB::FPEXT_F64_F128, "_Q_dtoq");
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setLibcallName(RTLIB::FPROUND_F128_F32, "_Q_qtos");
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setLibcallName(RTLIB::FPROUND_F128_F64, "_Q_qtod");
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}
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}
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setMinFunctionAlignment(2);
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@ -1605,23 +1665,264 @@ SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op,
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return makeAddress(Op, DAG);
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}
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static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
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SDValue
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SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args,
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SDValue Arg, SDLoc DL,
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SelectionDAG &DAG) const {
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MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
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EVT ArgVT = Arg.getValueType();
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Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
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ArgListEntry Entry;
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Entry.Node = Arg;
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Entry.Ty = ArgTy;
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if (ArgTy->isFP128Ty()) {
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// Create a stack object and pass the pointer to the library function.
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int FI = MFI->CreateStackObject(16, 8, false);
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SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
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Chain = DAG.getStore(Chain,
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DL,
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Entry.Node,
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FIPtr,
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MachinePointerInfo(),
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false,
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false,
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8);
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Entry.Node = FIPtr;
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Entry.Ty = PointerType::getUnqual(ArgTy);
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}
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Args.push_back(Entry);
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return Chain;
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}
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SDValue
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SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG,
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const char *LibFuncName,
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unsigned numArgs) const {
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ArgListTy Args;
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MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
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SDValue Callee = DAG.getExternalSymbol(LibFuncName, getPointerTy());
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Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
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Type *RetTyABI = RetTy;
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SDValue Chain = DAG.getEntryNode();
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SDValue RetPtr;
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if (RetTy->isFP128Ty()) {
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// Create a Stack Object to receive the return value of type f128.
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ArgListEntry Entry;
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int RetFI = MFI->CreateStackObject(16, 8, false);
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RetPtr = DAG.getFrameIndex(RetFI, getPointerTy());
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Entry.Node = RetPtr;
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Entry.Ty = PointerType::getUnqual(RetTy);
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if (!Subtarget->is64Bit())
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Entry.isSRet = true;
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Entry.isReturned = false;
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Args.push_back(Entry);
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RetTyABI = Type::getVoidTy(*DAG.getContext());
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}
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assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
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for (unsigned i = 0, e = numArgs; i != e; ++i) {
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Chain = LowerF128_LibCallArg(Chain, Args, Op.getOperand(i), SDLoc(Op), DAG);
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}
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TargetLowering::
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CallLoweringInfo CLI(Chain,
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RetTyABI,
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false, false, false, false,
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0, CallingConv::C,
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false, false, true,
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Callee, Args, DAG, SDLoc(Op));
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std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
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// chain is in second result.
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if (RetTyABI == RetTy)
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return CallInfo.first;
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assert (RetTy->isFP128Ty() && "Unexpected return type!");
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Chain = CallInfo.second;
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// Load RetPtr to get the return value.
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return DAG.getLoad(Op.getValueType(),
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SDLoc(Op),
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Chain,
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RetPtr,
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MachinePointerInfo(),
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false, false, false, 8);
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}
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SDValue
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SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
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unsigned &SPCC,
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SDLoc DL,
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SelectionDAG &DAG) const {
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const char *LibCall = 0;
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bool is64Bit = Subtarget->is64Bit();
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switch(SPCC) {
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default: llvm_unreachable("Unhandled conditional code!");
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case SPCC::FCC_E : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break;
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case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break;
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case SPCC::FCC_L : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break;
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case SPCC::FCC_G : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break;
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case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break;
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case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break;
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case SPCC::FCC_UL :
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case SPCC::FCC_ULE:
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case SPCC::FCC_UG :
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case SPCC::FCC_UGE:
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case SPCC::FCC_U :
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case SPCC::FCC_O :
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case SPCC::FCC_LG :
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case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break;
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}
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SDValue Callee = DAG.getExternalSymbol(LibCall, getPointerTy());
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Type *RetTy = Type::getInt32Ty(*DAG.getContext());
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ArgListTy Args;
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SDValue Chain = DAG.getEntryNode();
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Chain = LowerF128_LibCallArg(Chain, Args, LHS, DL, DAG);
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Chain = LowerF128_LibCallArg(Chain, Args, RHS, DL, DAG);
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TargetLowering::
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CallLoweringInfo CLI(Chain,
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RetTy,
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false, false, false, false,
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0, CallingConv::C,
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false, false, true,
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Callee, Args, DAG, DL);
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std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
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// result is in first, and chain is in second result.
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SDValue Result = CallInfo.first;
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switch(SPCC) {
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default: {
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SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
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SPCC = SPCC::ICC_NE;
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return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
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}
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case SPCC::FCC_UL : {
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SDValue Mask = DAG.getTargetConstant(1, Result.getValueType());
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Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
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SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
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SPCC = SPCC::ICC_NE;
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return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
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}
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case SPCC::FCC_ULE: {
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SDValue RHS = DAG.getTargetConstant(2, LHS.getValueType());
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SPCC = SPCC::ICC_NE;
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return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
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}
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case SPCC::FCC_UG : {
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SDValue RHS = DAG.getTargetConstant(1, Result.getValueType());
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SPCC = SPCC::ICC_G;
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return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
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}
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case SPCC::FCC_UGE: {
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SDValue RHS = DAG.getTargetConstant(1, Result.getValueType());
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SPCC = SPCC::ICC_NE;
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return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
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}
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case SPCC::FCC_U : {
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SDValue RHS = DAG.getTargetConstant(3, Result.getValueType());
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SPCC = SPCC::ICC_E;
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return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
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}
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case SPCC::FCC_O : {
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SDValue RHS = DAG.getTargetConstant(3, Result.getValueType());
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SPCC = SPCC::ICC_NE;
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return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
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}
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case SPCC::FCC_LG : {
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SDValue Mask = DAG.getTargetConstant(3, Result.getValueType());
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Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
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SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
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SPCC = SPCC::ICC_NE;
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return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
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}
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case SPCC::FCC_UE : {
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SDValue Mask = DAG.getTargetConstant(3, Result.getValueType());
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Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
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SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
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SPCC = SPCC::ICC_E;
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return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
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}
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}
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}
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static SDValue
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LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG,
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const SparcTargetLowering &TLI) {
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if (Op.getOperand(0).getValueType() == MVT::f64)
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return TLI.LowerF128Op(Op, DAG,
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TLI.getLibcallName(RTLIB::FPEXT_F64_F128), 1);
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if (Op.getOperand(0).getValueType() == MVT::f32)
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return TLI.LowerF128Op(Op, DAG,
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TLI.getLibcallName(RTLIB::FPEXT_F32_F128), 1);
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llvm_unreachable("fpextend with non-float operand!");
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return SDValue(0, 0);
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}
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static SDValue
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LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG,
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const SparcTargetLowering &TLI) {
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// FP_ROUND on f64 and f32 are legal.
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if (Op.getOperand(0).getValueType() != MVT::f128)
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return Op;
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if (Op.getValueType() == MVT::f64)
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return TLI.LowerF128Op(Op, DAG,
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TLI.getLibcallName(RTLIB::FPROUND_F128_F64), 1);
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if (Op.getValueType() == MVT::f32)
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return TLI.LowerF128Op(Op, DAG,
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TLI.getLibcallName(RTLIB::FPROUND_F128_F32), 1);
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llvm_unreachable("fpround to non-float!");
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return SDValue(0, 0);
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}
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static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
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const SparcTargetLowering &TLI,
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bool hasHardQuad) {
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SDLoc dl(Op);
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// Convert the fp value to integer in an FP register.
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assert(Op.getValueType() == MVT::i32);
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if (Op.getOperand(0).getValueType() == MVT::f128 && !hasHardQuad)
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return TLI.LowerF128Op(Op, DAG,
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TLI.getLibcallName(RTLIB::FPTOSINT_F128_I32), 1);
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Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
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return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
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}
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static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
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static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
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const SparcTargetLowering &TLI,
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bool hasHardQuad) {
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SDLoc dl(Op);
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assert(Op.getOperand(0).getValueType() == MVT::i32);
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SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
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// Convert the int value to FP in an FP register.
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if (Op.getValueType() == MVT::f128 && hasHardQuad)
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return TLI.LowerF128Op(Op, DAG,
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TLI.getLibcallName(RTLIB::SINTTOFP_I32_F128), 1);
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return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp);
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}
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static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
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static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
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const SparcTargetLowering &TLI,
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bool hasHardQuad) {
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SDValue Chain = Op.getOperand(0);
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
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SDValue LHS = Op.getOperand(2);
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@ -1642,15 +1943,23 @@ static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
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// 32-bit compares use the icc flags, 64-bit uses the xcc flags.
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Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC;
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} else {
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CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
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if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
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Opc = SPISD::BRFCC;
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if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
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if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
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CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
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Opc = SPISD::BRICC;
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} else {
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CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
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if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
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Opc = SPISD::BRFCC;
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}
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}
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return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
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DAG.getConstant(SPCC, MVT::i32), CompareFlag);
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}
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static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
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static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
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const SparcTargetLowering &TLI,
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bool hasHardQuad) {
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
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@ -1670,9 +1979,15 @@ static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
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SPISD::SELECT_ICC : SPISD::SELECT_XCC;
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if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
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} else {
|
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CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
|
||||
Opc = SPISD::SELECT_FCC;
|
||||
if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
|
||||
if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
|
||||
if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
|
||||
CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
|
||||
Opc = SPISD::SELECT_ICC;
|
||||
} else {
|
||||
CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
|
||||
Opc = SPISD::SELECT_FCC;
|
||||
if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
|
||||
}
|
||||
}
|
||||
return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
|
||||
DAG.getConstant(SPCC, MVT::i32), CompareFlag);
|
||||
@ -1931,14 +2246,57 @@ static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
|
||||
&OutChains[0], 2);
|
||||
}
|
||||
|
||||
static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG,
|
||||
const SparcTargetLowering &TLI,
|
||||
bool is64Bit) {
|
||||
if (Op.getValueType() == MVT::f64)
|
||||
return LowerF64Op(Op, DAG);
|
||||
if (Op.getValueType() == MVT::f128)
|
||||
return TLI.LowerF128Op(Op, DAG, ((is64Bit) ? "_Qp_neg" : "_Q_neg"), 1);
|
||||
return Op;
|
||||
}
|
||||
|
||||
static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
|
||||
if (Op.getValueType() == MVT::f64)
|
||||
return LowerF64Op(Op, DAG);
|
||||
if (Op.getValueType() != MVT::f128)
|
||||
return Op;
|
||||
|
||||
// Lower fabs on f128 to fabs on f64
|
||||
// fabs f128 => fabs f64:sub_even64, fmov f64:sub_odd64
|
||||
|
||||
SDLoc dl(Op);
|
||||
SDValue SrcReg128 = Op.getOperand(0);
|
||||
SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64,
|
||||
SrcReg128);
|
||||
SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64,
|
||||
SrcReg128);
|
||||
if (isV9)
|
||||
Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64);
|
||||
else
|
||||
Hi64 = LowerF64Op(Op, DAG);
|
||||
|
||||
SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
|
||||
dl, MVT::f128), 0);
|
||||
DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128,
|
||||
DstReg128, Hi64);
|
||||
DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128,
|
||||
DstReg128, Lo64);
|
||||
return DstReg128;
|
||||
}
|
||||
|
||||
|
||||
|
||||
SDValue SparcTargetLowering::
|
||||
LowerOperation(SDValue Op, SelectionDAG &DAG) const {
|
||||
|
||||
bool hasHardQuad = Subtarget->hasHardQuad();
|
||||
bool is64Bit = Subtarget->is64Bit();
|
||||
bool isV9 = Subtarget->isV9();
|
||||
|
||||
switch (Op.getOpcode()) {
|
||||
default: llvm_unreachable("Should not custom lower this!");
|
||||
|
||||
case ISD::FNEG:
|
||||
case ISD::FABS: return LowerF64Op(Op, DAG);
|
||||
|
||||
case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, *this);
|
||||
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
|
||||
case ISD::GlobalTLSAddress:
|
||||
@ -1946,16 +2304,34 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const {
|
||||
case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
|
||||
case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
|
||||
case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
|
||||
case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
|
||||
case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
|
||||
case ISD::BR_CC: return LowerBR_CC(Op, DAG);
|
||||
case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
|
||||
case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this,
|
||||
hasHardQuad);
|
||||
case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this,
|
||||
hasHardQuad);
|
||||
case ISD::BR_CC: return LowerBR_CC(Op, DAG, *this,
|
||||
hasHardQuad);
|
||||
case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this,
|
||||
hasHardQuad);
|
||||
case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
|
||||
case ISD::VAARG: return LowerVAARG(Op, DAG);
|
||||
case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
|
||||
|
||||
case ISD::LOAD: return LowerF128Load(Op, DAG);
|
||||
case ISD::STORE: return LowerF128Store(Op, DAG);
|
||||
case ISD::FADD: return LowerF128Op(Op, DAG,
|
||||
getLibcallName(RTLIB::ADD_F128), 2);
|
||||
case ISD::FSUB: return LowerF128Op(Op, DAG,
|
||||
getLibcallName(RTLIB::SUB_F128), 2);
|
||||
case ISD::FMUL: return LowerF128Op(Op, DAG,
|
||||
getLibcallName(RTLIB::MUL_F128), 2);
|
||||
case ISD::FDIV: return LowerF128Op(Op, DAG,
|
||||
getLibcallName(RTLIB::DIV_F128), 2);
|
||||
case ISD::FSQRT: return LowerF128Op(Op, DAG,
|
||||
getLibcallName(RTLIB::SQRT_F128),1);
|
||||
case ISD::FNEG: return LowerFNEG(Op, DAG, *this, is64Bit);
|
||||
case ISD::FABS: return LowerFABS(Op, DAG, isV9);
|
||||
case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this);
|
||||
case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1972,11 +2348,13 @@ SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
||||
case SP::SELECT_CC_Int_ICC:
|
||||
case SP::SELECT_CC_FP_ICC:
|
||||
case SP::SELECT_CC_DFP_ICC:
|
||||
case SP::SELECT_CC_QFP_ICC:
|
||||
BROpcode = SP::BCOND;
|
||||
break;
|
||||
case SP::SELECT_CC_Int_FCC:
|
||||
case SP::SELECT_CC_FP_FCC:
|
||||
case SP::SELECT_CC_DFP_FCC:
|
||||
case SP::SELECT_CC_QFP_FCC:
|
||||
BROpcode = SP::FBCOND;
|
||||
break;
|
||||
}
|
||||
|
||||
@ -127,6 +127,23 @@ namespace llvm {
|
||||
SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
|
||||
SelectionDAG &DAG) const;
|
||||
SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
|
||||
|
||||
SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args,
|
||||
SDValue Arg, SDLoc DL,
|
||||
SelectionDAG &DAG) const;
|
||||
SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG,
|
||||
const char *LibFuncName,
|
||||
unsigned numArgs) const;
|
||||
SDValue LowerF128Compare(SDValue LHS, SDValue RHS,
|
||||
unsigned &SPCC,
|
||||
SDLoc DL,
|
||||
SelectionDAG &DAG) const;
|
||||
|
||||
bool ShouldShrinkFPConstant(EVT VT) const {
|
||||
// Do not shrink FP constpool if VT == MVT::f128.
|
||||
// (ldd, call _Q_fdtoq) is more expensive than two ldds.
|
||||
return VT != MVT::f128;
|
||||
}
|
||||
};
|
||||
} // end namespace llvm
|
||||
|
||||
|
||||
@ -267,6 +267,11 @@ let Uses = [ICC], usesCustomInserter = 1 in {
|
||||
: Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
|
||||
"; SELECT_CC_DFP_ICC PSEUDO!",
|
||||
[(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>;
|
||||
|
||||
def SELECT_CC_QFP_ICC
|
||||
: Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
|
||||
"; SELECT_CC_QFP_ICC PSEUDO!",
|
||||
[(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
|
||||
}
|
||||
|
||||
let usesCustomInserter = 1, Uses = [FCC] in {
|
||||
@ -284,6 +289,10 @@ let usesCustomInserter = 1, Uses = [FCC] in {
|
||||
: Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
|
||||
"; SELECT_CC_DFP_FCC PSEUDO!",
|
||||
[(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;
|
||||
def SELECT_CC_QFP_FCC
|
||||
: Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
|
||||
"; SELECT_CC_QFP_FCC PSEUDO!",
|
||||
[(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -1,16 +1,30 @@
|
||||
; RUN: llc < %s -march=sparc -mattr=hard-quad-float | FileCheck %s
|
||||
; RUN: llc < %s -march=sparc -mattr=hard-quad-float | FileCheck %s --check-prefix=HARD
|
||||
; RUN: llc < %s -march=sparc -mattr=-hard-quad-float | FileCheck %s --check-prefix=SOFT
|
||||
|
||||
; CHECK-LABEL: f128_ops
|
||||
; CHECK: ldd
|
||||
; CHECK: ldd
|
||||
; CHECK: ldd
|
||||
; CHECK: ldd
|
||||
; CHECK: faddq [[R0:.+]], [[R1:.+]], [[R2:.+]]
|
||||
; CHECK: fsubq [[R2]], [[R3:.+]], [[R4:.+]]
|
||||
; CHECK: fmulq [[R4]], [[R5:.+]], [[R6:.+]]
|
||||
; CHECK: fdivq [[R6]], [[R2]]
|
||||
; CHECK: std
|
||||
; CHECK: std
|
||||
|
||||
; HARD-LABEL: f128_ops
|
||||
; HARD: ldd
|
||||
; HARD: ldd
|
||||
; HARD: ldd
|
||||
; HARD: ldd
|
||||
; HARD: faddq [[R0:.+]], [[R1:.+]], [[R2:.+]]
|
||||
; HARD: fsubq [[R2]], [[R3:.+]], [[R4:.+]]
|
||||
; HARD: fmulq [[R4]], [[R5:.+]], [[R6:.+]]
|
||||
; HARD: fdivq [[R6]], [[R2]]
|
||||
; HARD: std
|
||||
; HARD: std
|
||||
|
||||
; SOFT-LABEL: f128_ops
|
||||
; SOFT: ldd
|
||||
; SOFT: ldd
|
||||
; SOFT: ldd
|
||||
; SOFT: ldd
|
||||
; SOFT: call _Q_add
|
||||
; SOFT: call _Q_sub
|
||||
; SOFT: call _Q_mul
|
||||
; SOFT: call _Q_div
|
||||
; SOFT: std
|
||||
; SOFT: std
|
||||
|
||||
define void @f128_ops(fp128* noalias sret %scalar.result, fp128* byval %a, fp128* byval %b, fp128* byval %c, fp128* byval %d) {
|
||||
entry:
|
||||
@ -26,12 +40,19 @@ entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: f128_spill
|
||||
; CHECK: std %f{{.+}}, [%[[S0:.+]]]
|
||||
; CHECK: std %f{{.+}}, [%[[S1:.+]]]
|
||||
; CHECK-DAG: ldd [%[[S0]]], %f{{.+}}
|
||||
; CHECK-DAG: ldd [%[[S1]]], %f{{.+}}
|
||||
; CHECK: jmp
|
||||
; HARD-LABEL: f128_spill
|
||||
; HARD: std %f{{.+}}, [%[[S0:.+]]]
|
||||
; HARD: std %f{{.+}}, [%[[S1:.+]]]
|
||||
; HARD-DAG: ldd [%[[S0]]], %f{{.+}}
|
||||
; HARD-DAG: ldd [%[[S1]]], %f{{.+}}
|
||||
; HARD: jmp
|
||||
|
||||
; SOFT-LABEL: f128_spill
|
||||
; SOFT: std %f{{.+}}, [%[[S0:.+]]]
|
||||
; SOFT: std %f{{.+}}, [%[[S1:.+]]]
|
||||
; SOFT-DAG: ldd [%[[S0]]], %f{{.+}}
|
||||
; SOFT-DAG: ldd [%[[S1]]], %f{{.+}}
|
||||
; SOFT: jmp
|
||||
|
||||
define void @f128_spill(fp128* noalias sret %scalar.result, fp128* byval %a) {
|
||||
entry:
|
||||
@ -40,3 +61,18 @@ entry:
|
||||
store fp128 %0, fp128* %scalar.result, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; HARD-LABEL: f128_compare
|
||||
; HARD: fcmpq
|
||||
|
||||
; SOFT-LABEL: f128_compare
|
||||
; SOFT: _Q_cmp
|
||||
|
||||
define i32 @f128_compare(fp128* byval %f0, fp128* byval %f1, i32 %a, i32 %b) {
|
||||
entry:
|
||||
%0 = load fp128* %f0, align 8
|
||||
%1 = load fp128* %f1, align 8
|
||||
%cond = fcmp ult fp128 %0, %1
|
||||
%ret = select i1 %cond, i32 %a, i32 %b
|
||||
ret i32 %ret
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user