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* Add new "Target Specific Flags" field to instruction descriptor
* Rename iclass to Flags git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4439 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -62,11 +62,12 @@ struct MachineInstrDescriptor {
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int resultPos; // Position of the result; -1 if no result
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unsigned maxImmedConst; // Largest +ve constant in IMMMED field or 0.
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bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
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// smallest -ve value is -(maxImmedConst+1).
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// smallest -ve value is -(maxImmedConst+1).
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unsigned numDelaySlots; // Number of delay slots after instruction
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unsigned latency; // Latency in machine cycles
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InstrSchedClass schedClass; // enum identifying instr sched class
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unsigned iclass; // flags identifying machine instr class
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unsigned latency; // Latency in machine cycles
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InstrSchedClass schedClass; // enum identifying instr sched class
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unsigned Flags; // flags identifying machine instr class
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unsigned TSFlags; // Target Specific Flag values
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};
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@ -117,67 +118,64 @@ public:
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// Query instruction class flags according to the machine-independent
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// flags listed above.
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//
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unsigned getIClass(MachineOpCode opCode) const {
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return get(opCode).iclass;
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}
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bool isNop(MachineOpCode opCode) const {
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return get(opCode).iclass & M_NOP_FLAG;
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return get(opCode).Flags & M_NOP_FLAG;
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}
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bool isBranch(MachineOpCode opCode) const {
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return get(opCode).iclass & M_BRANCH_FLAG;
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return get(opCode).Flags & M_BRANCH_FLAG;
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}
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bool isCall(MachineOpCode opCode) const {
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return get(opCode).iclass & M_CALL_FLAG;
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return get(opCode).Flags & M_CALL_FLAG;
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}
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bool isReturn(MachineOpCode opCode) const {
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return get(opCode).iclass & M_RET_FLAG;
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return get(opCode).Flags & M_RET_FLAG;
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}
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bool isControlFlow(MachineOpCode opCode) const {
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return get(opCode).iclass & M_BRANCH_FLAG
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|| get(opCode).iclass & M_CALL_FLAG
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|| get(opCode).iclass & M_RET_FLAG;
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return get(opCode).Flags & M_BRANCH_FLAG
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|| get(opCode).Flags & M_CALL_FLAG
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|| get(opCode).Flags & M_RET_FLAG;
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}
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bool isArith(MachineOpCode opCode) const {
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return get(opCode).iclass & M_ARITH_FLAG;
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return get(opCode).Flags & M_ARITH_FLAG;
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}
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bool isCCInstr(MachineOpCode opCode) const {
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return get(opCode).iclass & M_CC_FLAG;
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return get(opCode).Flags & M_CC_FLAG;
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}
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bool isLogical(MachineOpCode opCode) const {
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return get(opCode).iclass & M_LOGICAL_FLAG;
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return get(opCode).Flags & M_LOGICAL_FLAG;
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}
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bool isIntInstr(MachineOpCode opCode) const {
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return get(opCode).iclass & M_INT_FLAG;
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return get(opCode).Flags & M_INT_FLAG;
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}
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bool isFloatInstr(MachineOpCode opCode) const {
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return get(opCode).iclass & M_FLOAT_FLAG;
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return get(opCode).Flags & M_FLOAT_FLAG;
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}
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bool isConditional(MachineOpCode opCode) const {
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return get(opCode).iclass & M_CONDL_FLAG;
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return get(opCode).Flags & M_CONDL_FLAG;
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}
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bool isLoad(MachineOpCode opCode) const {
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return get(opCode).iclass & M_LOAD_FLAG;
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return get(opCode).Flags & M_LOAD_FLAG;
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}
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bool isPrefetch(MachineOpCode opCode) const {
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return get(opCode).iclass & M_PREFETCH_FLAG;
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return get(opCode).Flags & M_PREFETCH_FLAG;
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}
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bool isLoadOrPrefetch(MachineOpCode opCode) const {
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return get(opCode).iclass & M_LOAD_FLAG
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|| get(opCode).iclass & M_PREFETCH_FLAG;
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return get(opCode).Flags & M_LOAD_FLAG
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|| get(opCode).Flags & M_PREFETCH_FLAG;
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}
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bool isStore(MachineOpCode opCode) const {
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return get(opCode).iclass & M_STORE_FLAG;
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return get(opCode).Flags & M_STORE_FLAG;
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}
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bool isMemoryAccess(MachineOpCode opCode) const {
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return get(opCode).iclass & M_LOAD_FLAG
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|| get(opCode).iclass & M_PREFETCH_FLAG
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|| get(opCode).iclass & M_STORE_FLAG;
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return get(opCode).Flags & M_LOAD_FLAG
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|| get(opCode).Flags & M_PREFETCH_FLAG
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|| get(opCode).Flags & M_STORE_FLAG;
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}
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bool isDummyPhiInstr(const MachineOpCode opCode) const {
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return get(opCode).iclass & M_DUMMY_PHI_FLAG;
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return get(opCode).Flags & M_DUMMY_PHI_FLAG;
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}
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bool isPseudoInstr(const MachineOpCode opCode) const {
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return get(opCode).iclass & M_PSEUDO_FLAG;
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return get(opCode).Flags & M_PSEUDO_FLAG;
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}
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// Check if an instruction can be issued before its operands are ready,
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@ -62,11 +62,12 @@ struct MachineInstrDescriptor {
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int resultPos; // Position of the result; -1 if no result
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unsigned maxImmedConst; // Largest +ve constant in IMMMED field or 0.
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bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
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// smallest -ve value is -(maxImmedConst+1).
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// smallest -ve value is -(maxImmedConst+1).
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unsigned numDelaySlots; // Number of delay slots after instruction
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unsigned latency; // Latency in machine cycles
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InstrSchedClass schedClass; // enum identifying instr sched class
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unsigned iclass; // flags identifying machine instr class
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unsigned latency; // Latency in machine cycles
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InstrSchedClass schedClass; // enum identifying instr sched class
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unsigned Flags; // flags identifying machine instr class
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unsigned TSFlags; // Target Specific Flag values
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};
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@ -117,67 +118,64 @@ public:
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// Query instruction class flags according to the machine-independent
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// flags listed above.
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//
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unsigned getIClass(MachineOpCode opCode) const {
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return get(opCode).iclass;
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}
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bool isNop(MachineOpCode opCode) const {
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return get(opCode).iclass & M_NOP_FLAG;
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return get(opCode).Flags & M_NOP_FLAG;
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}
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bool isBranch(MachineOpCode opCode) const {
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return get(opCode).iclass & M_BRANCH_FLAG;
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return get(opCode).Flags & M_BRANCH_FLAG;
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}
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bool isCall(MachineOpCode opCode) const {
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return get(opCode).iclass & M_CALL_FLAG;
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return get(opCode).Flags & M_CALL_FLAG;
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}
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bool isReturn(MachineOpCode opCode) const {
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return get(opCode).iclass & M_RET_FLAG;
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return get(opCode).Flags & M_RET_FLAG;
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}
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bool isControlFlow(MachineOpCode opCode) const {
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return get(opCode).iclass & M_BRANCH_FLAG
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|| get(opCode).iclass & M_CALL_FLAG
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|| get(opCode).iclass & M_RET_FLAG;
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return get(opCode).Flags & M_BRANCH_FLAG
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|| get(opCode).Flags & M_CALL_FLAG
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|| get(opCode).Flags & M_RET_FLAG;
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}
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bool isArith(MachineOpCode opCode) const {
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return get(opCode).iclass & M_ARITH_FLAG;
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return get(opCode).Flags & M_ARITH_FLAG;
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}
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bool isCCInstr(MachineOpCode opCode) const {
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return get(opCode).iclass & M_CC_FLAG;
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return get(opCode).Flags & M_CC_FLAG;
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}
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bool isLogical(MachineOpCode opCode) const {
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return get(opCode).iclass & M_LOGICAL_FLAG;
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return get(opCode).Flags & M_LOGICAL_FLAG;
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}
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bool isIntInstr(MachineOpCode opCode) const {
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return get(opCode).iclass & M_INT_FLAG;
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return get(opCode).Flags & M_INT_FLAG;
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}
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bool isFloatInstr(MachineOpCode opCode) const {
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return get(opCode).iclass & M_FLOAT_FLAG;
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return get(opCode).Flags & M_FLOAT_FLAG;
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}
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bool isConditional(MachineOpCode opCode) const {
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return get(opCode).iclass & M_CONDL_FLAG;
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return get(opCode).Flags & M_CONDL_FLAG;
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}
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bool isLoad(MachineOpCode opCode) const {
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return get(opCode).iclass & M_LOAD_FLAG;
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return get(opCode).Flags & M_LOAD_FLAG;
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}
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bool isPrefetch(MachineOpCode opCode) const {
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return get(opCode).iclass & M_PREFETCH_FLAG;
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return get(opCode).Flags & M_PREFETCH_FLAG;
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}
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bool isLoadOrPrefetch(MachineOpCode opCode) const {
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return get(opCode).iclass & M_LOAD_FLAG
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|| get(opCode).iclass & M_PREFETCH_FLAG;
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return get(opCode).Flags & M_LOAD_FLAG
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|| get(opCode).Flags & M_PREFETCH_FLAG;
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}
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bool isStore(MachineOpCode opCode) const {
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return get(opCode).iclass & M_STORE_FLAG;
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return get(opCode).Flags & M_STORE_FLAG;
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}
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bool isMemoryAccess(MachineOpCode opCode) const {
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return get(opCode).iclass & M_LOAD_FLAG
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|| get(opCode).iclass & M_PREFETCH_FLAG
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|| get(opCode).iclass & M_STORE_FLAG;
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return get(opCode).Flags & M_LOAD_FLAG
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|| get(opCode).Flags & M_PREFETCH_FLAG
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|| get(opCode).Flags & M_STORE_FLAG;
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}
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bool isDummyPhiInstr(const MachineOpCode opCode) const {
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return get(opCode).iclass & M_DUMMY_PHI_FLAG;
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return get(opCode).Flags & M_DUMMY_PHI_FLAG;
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}
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bool isPseudoInstr(const MachineOpCode opCode) const {
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return get(opCode).iclass & M_PSEUDO_FLAG;
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return get(opCode).Flags & M_PSEUDO_FLAG;
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}
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// Check if an instruction can be issued before its operands are ready,
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