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Fix indentation and wrap code at 80 cols

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15107 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman
2004-07-22 15:26:23 +00:00
parent d3014edc51
commit 75fa4e4f99
1 changed files with 89 additions and 99 deletions
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188
lib/CodeGen/TwoAddressInstructionPass.cpp
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@ -43,133 +43,123 @@
using namespace llvm; using namespace llvm;
namespace { namespace {
Statistic<> numTwoAddressInstrs("twoaddressinstruction", Statistic<> numTwoAddressInstrs("twoaddressinstruction",
"Number of two-address instructions"); "Number of two-address instructions");
Statistic<> numInstrsAdded("twoaddressinstruction", Statistic<> numInstrsAdded("twoaddressinstruction",
"Number of instructions added"); "Number of instructions added");
struct TwoAddressInstructionPass : public MachineFunctionPass struct TwoAddressInstructionPass : public MachineFunctionPass {
{ virtual void getAnalysisUsage(AnalysisUsage &AU) const;
virtual void getAnalysisUsage(AnalysisUsage &AU) const;
/// runOnMachineFunction - pass entry point /// runOnMachineFunction - pass entry point
bool runOnMachineFunction(MachineFunction&); bool runOnMachineFunction(MachineFunction&);
}; };
RegisterPass<TwoAddressInstructionPass> X( RegisterPass<TwoAddressInstructionPass>
"twoaddressinstruction", "Two-Address instruction pass"); X("twoaddressinstruction", "Two-Address instruction pass");
}; };
const PassInfo *llvm::TwoAddressInstructionPassID = X.getPassInfo(); const PassInfo *llvm::TwoAddressInstructionPassID = X.getPassInfo();
void TwoAddressInstructionPass::getAnalysisUsage(AnalysisUsage &AU) const void TwoAddressInstructionPass::getAnalysisUsage(AnalysisUsage &AU) const {
{ AU.addPreserved<LiveVariables>();
AU.addPreserved<LiveVariables>(); AU.addPreservedID(PHIEliminationID);
AU.addPreservedID(PHIEliminationID); MachineFunctionPass::getAnalysisUsage(AU);
MachineFunctionPass::getAnalysisUsage(AU);
} }
/// runOnMachineFunction - Reduce two-address instructions to two /// runOnMachineFunction - Reduce two-address instructions to two
/// operands. /// operands.
/// ///
bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
DEBUG(std::cerr << "Machine Function\n"); DEBUG(std::cerr << "Machine Function\n");
const TargetMachine &TM = MF.getTarget(); const TargetMachine &TM = MF.getTarget();
const MRegisterInfo &MRI = *TM.getRegisterInfo(); const MRegisterInfo &MRI = *TM.getRegisterInfo();
const TargetInstrInfo &TII = *TM.getInstrInfo(); const TargetInstrInfo &TII = *TM.getInstrInfo();
LiveVariables* LV = getAnalysisToUpdate<LiveVariables>(); LiveVariables* LV = getAnalysisToUpdate<LiveVariables>();
bool MadeChange = false; bool MadeChange = false;
DEBUG(std::cerr << "********** REWRITING TWO-ADDR INSTRS **********\n"); DEBUG(std::cerr << "********** REWRITING TWO-ADDR INSTRS **********\n");
DEBUG(std::cerr << "********** Function: " DEBUG(std::cerr << "********** Function: "
<< MF.getFunction()->getName() << '\n'); << MF.getFunction()->getName() << '\n');
for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end(); for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
mbbi != mbbe; ++mbbi) { mbbi != mbbe; ++mbbi) {
for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end(); for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
mi != me; ++mi) { mi != me; ++mi) {
unsigned opcode = mi->getOpcode(); unsigned opcode = mi->getOpcode();
// ignore if it is not a two-address instruction // ignore if it is not a two-address instruction
if (!TII.isTwoAddrInstr(opcode)) if (!TII.isTwoAddrInstr(opcode))
continue; continue;
++numTwoAddressInstrs; ++numTwoAddressInstrs;
DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM));
assert(mi->getOperand(1).isRegister() && mi->getOperand(1).getReg() &&
mi->getOperand(1).isUse() && "two address instruction invalid");
DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM)); // if the two operands are the same we just remove the use
// and mark the def as def&use, otherwise we have to insert a copy.
if (mi->getOperand(0).getReg() != mi->getOperand(1).getReg()) {
// rewrite:
// a = b op c
// to:
// a = b
// a = a op c
unsigned regA = mi->getOperand(0).getReg();
unsigned regB = mi->getOperand(1).getReg();
assert(mi->getOperand(1).isRegister() && assert(MRegisterInfo::isVirtualRegister(regA) &&
mi->getOperand(1).getReg() && MRegisterInfo::isVirtualRegister(regB) &&
mi->getOperand(1).isUse() && "cannot update physical register live information");
"two address instruction invalid");
// if the two operands are the same we just remove the use // first make sure we do not have a use of a in the
// and mark the def as def&use, otherwise we have to insert a copy. // instruction (a = b + a for example) because our
if (mi->getOperand(0).getReg() != mi->getOperand(1).getReg()) { // transformation will not work. This should never occur
// rewrite: // because we are in SSA form.
// a = b op c
// to:
// a = b
// a = a op c
unsigned regA = mi->getOperand(0).getReg();
unsigned regB = mi->getOperand(1).getReg();
assert(MRegisterInfo::isVirtualRegister(regA) &&
MRegisterInfo::isVirtualRegister(regB) &&
"cannot update physical register live information");
// first make sure we do not have a use of a in the
// instruction (a = b + a for example) because our
// transformation will not work. This should never occur
// because we are in SSA form.
#ifndef NDEBUG #ifndef NDEBUG
for (unsigned i = 1; i != mi->getNumOperands(); ++i) for (unsigned i = 1; i != mi->getNumOperands(); ++i)
assert(!mi->getOperand(i).isRegister() || assert(!mi->getOperand(i).isRegister() ||
mi->getOperand(i).getReg() != regA); mi->getOperand(i).getReg() != regA);
#endif #endif
const TargetRegisterClass* rc = const TargetRegisterClass* rc = MF.getSSARegMap()->getRegClass(regA);
MF.getSSARegMap()->getRegClass(regA); unsigned Added = MRI.copyRegToReg(*mbbi, mi, regA, regB, rc);
unsigned Added = MRI.copyRegToReg(*mbbi, mi, regA, regB, rc); numInstrsAdded += Added;
numInstrsAdded += Added;
MachineBasicBlock::iterator prevMi = prior(mi); MachineBasicBlock::iterator prevMi = prior(mi);
DEBUG(std::cerr << "\t\tprepend:\t"; DEBUG(std::cerr << "\t\tprepend:\t"; prevMi->print(std::cerr, &TM));
prevMi->print(std::cerr, &TM));
if (LV) { if (LV) {
// update live variables for regA // update live variables for regA
assert(Added == 1 && assert(Added == 1 && "Cannot handle multi-instruction copies yet!");
"Cannot handle multi-instruction copies yet!"); LiveVariables::VarInfo& varInfo = LV->getVarInfo(regA);
LiveVariables::VarInfo& varInfo = LV->getVarInfo(regA); varInfo.DefInst = prevMi;
varInfo.DefInst = prevMi;
// update live variables for regB // update live variables for regB
if (LV->removeVirtualRegisterKilled(regB, mbbi, mi)) if (LV->removeVirtualRegisterKilled(regB, mbbi, mi))
LV->addVirtualRegisterKilled(regB, prevMi); LV->addVirtualRegisterKilled(regB, prevMi);
if (LV->removeVirtualRegisterDead(regB, mbbi, mi)) if (LV->removeVirtualRegisterDead(regB, mbbi, mi))
LV->addVirtualRegisterDead(regB, prevMi); LV->addVirtualRegisterDead(regB, prevMi);
}
// replace all occurences of regB with regA
for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) {
if (mi->getOperand(i).isRegister() &&
mi->getOperand(i).getReg() == regB)
mi->SetMachineOperandReg(i, regA);
}
}
assert(mi->getOperand(0).isDef());
mi->getOperand(0).setUse();
mi->RemoveOperand(1);
MadeChange = true;
DEBUG(std::cerr << "\t\trewrite to:\t";
mi->print(std::cerr, &TM));
} }
}
return MadeChange; // replace all occurences of regB with regA
for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) {
if (mi->getOperand(i).isRegister() &&
mi->getOperand(i).getReg() == regB)
mi->SetMachineOperandReg(i, regA);
}
}
assert(mi->getOperand(0).isDef());
mi->getOperand(0).setUse();
mi->RemoveOperand(1);
MadeChange = true;
DEBUG(std::cerr << "\t\trewrite to:\t"; mi->print(std::cerr, &TM));
}
}
return MadeChange;
} }