6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-28 09:31:03 +00:00
Code Issues Projects Releases Wiki Activity

fix store issue and an FP conversion (segfault) issue

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20066 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth 2005-02-07 23:02:23 +00:00
parent bcc70bcb25
commit 760270da51
2 changed files with 21 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/Target/Alpha/AlphaISelPattern.cpp
View File

@ -1164,6 +1164,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
void ISel::Select(SDOperand N) { void ISel::Select(SDOperand N) {
unsigned Tmp1, Tmp2, Opc; unsigned Tmp1, Tmp2, Opc;
unsigned opcode = N.getOpcode();
// FIXME: Disable for our current expansion model! // FIXME: Disable for our current expansion model!
if (/*!N->hasOneUse() &&*/ !ExprMap.insert(std::make_pair(N, notIn)).second) if (/*!N->hasOneUse() &&*/ !ExprMap.insert(std::make_pair(N, notIn)).second)
@ -1171,7 +1172,8 @@ void ISel::Select(SDOperand N) {
SDNode *Node = N.Val; SDNode *Node = N.Val;
switch (N.getOpcode()) {
switch (opcode) {
default: default:
Node->dump(); std::cerr << "\n"; Node->dump(); std::cerr << "\n";
@ -1267,16 +1269,24 @@ void ISel::Select(SDOperand N) {
Select(Chain); Select(Chain);
Tmp1 = SelectExpr(Value); //value Tmp1 = SelectExpr(Value); //value
if (opcode == ISD::STORE) {
switch(Value.getValueType()) { switch(Value.getValueType()) {
default: assert(0 && "unknown Type in store"); default: assert(0 && "unknown Type in store");
case MVT::i64: Opc = Alpha::STQ; break; case MVT::i64: Opc = Alpha::STQ; break;
case MVT::f64: Opc = Alpha::STT; break; case MVT::f64: Opc = Alpha::STT; break;
case MVT::f32: Opc = Alpha::STS; break; case MVT::f32: Opc = Alpha::STS; break;
}
} else { //ISD::TRUNCSTORE
switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
default: assert(0 && "unknown Type in store");
case MVT::i1: //FIXME: DAG does not promote this load case MVT::i1: //FIXME: DAG does not promote this load
case MVT::i8: Opc = Alpha::STB; break; case MVT::i8: Opc = Alpha::STB; break;
case MVT::i16: Opc = Alpha::STW; break; case MVT::i16: Opc = Alpha::STW; break;
case MVT::i32: Opc = Alpha::STL; break; case MVT::i32: Opc = Alpha::STL; break;
} }
}
if (Address.getOpcode() == ISD::GlobalAddress) if (Address.getOpcode() == ISD::GlobalAddress)
{ {
AlphaLowering.restoreGP(BB); AlphaLowering.restoreGP(BB);

2
lib/Target/Alpha/AlphaInstrInfo.td
View File

@ -358,7 +358,7 @@ def ITOFT : FPForm<0x14, 0x024, (ops FPRC:$RC, GPRC:$RA), "itoft $RA,$RC">; //In
//CVTQL F-P 17.030 Convert quadword to longword //CVTQL F-P 17.030 Convert quadword to longword
def CVTQS : FPForm<0x16, 0x0BC, (ops FPRC:$RC, FPRC:$RA), "cvtqs $RA,$RC">; //Convert quadword to S_floating def CVTQS : FPForm<0x16, 0x0BC, (ops FPRC:$RC, FPRC:$RA), "cvtqs $RA,$RC">; //Convert quadword to S_floating
def CVTQT : FPForm<0x16, 0x0BE, (ops FPRC:$RC, FPRC:$RA), "cvtqt $RA,$RC">; //Convert quadword to T_floating def CVTQT : FPForm<0x16, 0x0BE, (ops FPRC:$RC, FPRC:$RA), "cvtqt $RA,$RC">; //Convert quadword to T_floating
def CVTST : FPForm<0x16, 0x2AC, (ops FPRC:$RC, FPRC:$RA), "cvtst $RA,$RC">; //Convert S_floating to T_floating def CVTST : FPForm<0x16, 0x2AC, (ops FPRC:$RC, FPRC:$RA), "cvtsts $RA,$RC">; //Convert S_floating to T_floating (use completion, may not have function code for that set right)
def CVTTQ : FPForm<0x16, 0x0AF, (ops FPRC:$RC, FPRC:$RA), "cvttq $RA,$RC">; //Convert T_floating to quadword def CVTTQ : FPForm<0x16, 0x0AF, (ops FPRC:$RC, FPRC:$RA), "cvttq $RA,$RC">; //Convert T_floating to quadword
def CVTTS : FPForm<0x16, 0x2AC, (ops FPRC:$RC, FPRC:$RA), "cvtts $RA,$RC">; //Convert T_floating to S_floating def CVTTS : FPForm<0x16, 0x2AC, (ops FPRC:$RC, FPRC:$RA), "cvtts $RA,$RC">; //Convert T_floating to S_floating