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[ARM] Enable DP copy, load and store instructions for FPv4-SP

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The FPv4-SP floating-point unit is generally referred to as
single-precision only, but it does have double-precision registers and
load, store and GPR<->DPR move instructions which operate on them.
This patch enables the use of these registers, the main advantage of
which is that we now comply with the AAPCS-VFP calling convention.
This partially reverts r209650, which added some AAPCS-VFP support,
but did not handle return values or alignment of double arguments in
registers.

This patch also adds tests for Thumb2 code generation for
floating-point instructions and intrinsics, which previously only
existed for ARM.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216172 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Oliver Stannard
2014-08-21 12:50:31 +00:00
parent fc4bdcdc87
commit 760a46522a
15 changed files with 1280 additions and 66 deletions
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19
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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@@ -7265,8 +7265,11 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
}
if (Args[i].isNest)
Flags.setNest();
if (NeedsRegBlock)
if (NeedsRegBlock) {
Flags.setInConsecutiveRegs();
if (Value == NumValues - 1)
Flags.setInConsecutiveRegsLast();
}
Flags.setOrigAlign(OriginalAlignment);
MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
@@ -7312,10 +7315,6 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
else if (j != 0)
MyFlags.Flags.setOrigAlign(1);
// Only mark the end at the last register of the last value.
if (NeedsRegBlock && Value == NumValues - 1 && j == NumParts - 1)
MyFlags.Flags.setInConsecutiveRegsLast();
CLI.Outs.push_back(MyFlags);
CLI.OutVals.push_back(Parts[j]);
}
@@ -7530,8 +7529,11 @@ void SelectionDAGISel::LowerArguments(const Function &F) {
}
if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
Flags.setNest();
if (NeedsRegBlock)
if (NeedsRegBlock) {
Flags.setInConsecutiveRegs();
if (Value == NumValues - 1)
Flags.setInConsecutiveRegsLast();
}
Flags.setOrigAlign(OriginalAlignment);
MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
@@ -7544,11 +7546,6 @@ void SelectionDAGISel::LowerArguments(const Function &F) {
// if it isn't first piece, alignment must be 1
else if (i > 0)
MyFlags.Flags.setOrigAlign(1);
// Only mark the end at the last register of the last value.
if (NeedsRegBlock && Value == NumValues - 1 && i == NumRegs - 1)
MyFlags.Flags.setInConsecutiveRegsLast();
Ins.push_back(MyFlags);
}
PartBase += VT.getStoreSize();