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synced 2024-08-21 03:29:40 +00:00
Fix a couple of shuffle patterns to use movhlps instead
of movhps as the constraint. Changes optimizations so update testcases as appropriate as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86360 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2085,7 +2085,7 @@ def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
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[(set VR128:$dst, (v4i32 (pshufd:$src2
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(bc_v4i32(memopv2i64 addr:$src1)),
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(undef))))]>;
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}
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}
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// SSE2 with ImmT == Imm8 and XS prefix.
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def PSHUFHWri : Ii8<0x70, MRMSrcReg,
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@ -2874,7 +2874,7 @@ def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
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(PALIGNR128rr VR128:$src2, VR128:$src1,
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(SHUFFLE_get_palign_imm VR128:$src3))>,
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Requires<[HasSSSE3]>;
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}
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}
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def : Pat<(X86pshufb VR128:$src, VR128:$mask),
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(PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
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@ -3051,15 +3051,15 @@ def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
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let AddedComplexity = 20 in {
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// vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
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// vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
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// vector_shuffle v1, (load v2) <6, 7, 2, 3> using MOVHPS
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def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
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(MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
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def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
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(MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
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def : Pat<(v4f32 (movhp VR128:$src1, (load addr:$src2))),
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(MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
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def : Pat<(v2f64 (movhp VR128:$src1, (load addr:$src2))),
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(MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
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def : Pat<(v4f32 (movhlps (load addr:$src1), VR128:$src2)),
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(MOVHPSrm VR128:$src2, addr:$src1)>, Requires<[HasSSE1]>;
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def : Pat<(v2f64 (movhlps (load addr:$src1), VR128:$src2)),
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(MOVHPDrm VR128:$src2, addr:$src1)>, Requires<[HasSSE2]>;
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def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
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(MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
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@ -3077,9 +3077,9 @@ def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
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(MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
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def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
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(MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
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def : Pat<(store (v4f32 (movhp (load addr:$src1), VR128:$src2)), addr:$src1),
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def : Pat<(store (v4f32 (movhlps (load addr:$src1), VR128:$src2)), addr:$src1),
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(MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
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def : Pat<(store (v2f64 (movhp (load addr:$src1), VR128:$src2)), addr:$src1),
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def : Pat<(store (v2f64 (movhlps (load addr:$src1), VR128:$src2)), addr:$src1),
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(MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
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def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
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@ -145,7 +145,9 @@ define void @t9(<4 x float>* %r, <2 x i32>* %A) nounwind {
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ret void
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; X64: t9:
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; X64: movsd (%rsi), %xmm0
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; X64: movhps %xmm0, (%rdi)
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; X64: movaps (%rdi), %xmm1
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; X64: movlhps %xmm0, %xmm1
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; X64: movaps %xmm1, (%rdi)
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; X64: ret
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}
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@ -1,6 +1,6 @@
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; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t
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; RUN: grep movlhps %t | count 1
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; RUN: grep movhlps %t | count 1
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; RUN: grep movhps %t | count 1
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define <4 x float> @test1(<4 x float>* %x, <4 x float>* %y) {
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%tmp = load <4 x float>* %y ; <<4 x float>> [#uses=2]
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@ -18,4 +18,3 @@ entry:
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%tmp4 = shufflevector <4 x float> %tmp3, <4 x float> %tmp, <4 x i32> < i32 2, i32 3, i32 6, i32 7 > ; <<4 x float>> [#uses=1]
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ret <4 x float> %tmp4
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}
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