mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-26 23:29:22 +00:00
ARM: support struct byval in llvm
We handle struct byval by inserting a pseudo op, which will be expanded to a loop at ExpandISelPseudos. A separate patch for clang will be submitted to enable struct byval. rdar://9877866 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157793 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Manman Ren
parent
cdd6b2dca1
commit
763a75dbf7
@ -52,6 +52,7 @@ using namespace llvm;
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STATISTIC(NumTailCalls, "Number of tail calls");
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STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
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STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments");
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// This option should go away when tail calls fully work.
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static cl::opt<bool>
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@ -1424,21 +1425,21 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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CCInfo.clearFirstByValReg();
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}
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unsigned LocMemOffset = VA.getLocMemOffset();
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SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset);
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SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
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StkPtrOff);
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SDValue SrcOffset = DAG.getIntPtrConstant(4*offset);
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SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
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SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
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MVT::i32);
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MemOpChains.push_back(DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode,
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Flags.getByValAlign(),
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/*isVolatile=*/false,
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/*AlwaysInline=*/false,
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MachinePointerInfo(0),
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MachinePointerInfo(0)));
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if (Flags.getByValSize() - 4*offset > 0) {
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unsigned LocMemOffset = VA.getLocMemOffset();
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SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset);
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SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
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StkPtrOff);
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SDValue SrcOffset = DAG.getIntPtrConstant(4*offset);
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SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
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SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
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MVT::i32);
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SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
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SDValue Ops[] = { Chain, Dst, Src, SizeNode};
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MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
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Ops, array_lengthof(Ops)));
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}
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} else if (!IsSibCall) {
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assert(VA.isMemLoc());
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@ -6593,6 +6594,252 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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// return last added BB
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return SinkBB;
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}
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case ARM::COPY_STRUCT_BYVAL_I32: {
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++NumLoopByVals;
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// This pseudo instruction has 3 operands: dst, src, size
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// We expand it to a loop if size > Subtarget->getMaxInlineSizeThreshold().
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// Otherwise, we will generate unrolled scalar copies.
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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MachineFunction::iterator It = BB;
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++It;
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unsigned dest = MI->getOperand(0).getReg();
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unsigned src = MI->getOperand(1).getReg();
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unsigned size = MI->getOperand(2).getImm();
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DebugLoc dl = MI->getDebugLoc();
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unsigned BytesLeft = size & 3;
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unsigned LoopSize = size - BytesLeft;
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bool isThumb2 = Subtarget->isThumb2();
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MachineFunction *MF = BB->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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unsigned ldrOpc = isThumb2 ? ARM::t2LDR_POST : ARM::LDR_POST_IMM;
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unsigned strOpc = isThumb2 ? ARM::t2STR_POST : ARM::STR_POST_IMM;
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const TargetRegisterClass *TRC = isThumb2 ?
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(const TargetRegisterClass*)&ARM::tGPRRegClass :
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(const TargetRegisterClass*)&ARM::GPRRegClass;
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if (size <= Subtarget->getMaxInlineSizeThreshold()) {
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// Use LDR and STR to copy.
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// [scratch, srcOut] = LDR_POST(srcIn, 4)
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// [destOut] = STR_POST(scratch, destIn, 4)
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unsigned srcIn = src;
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unsigned destIn = dest;
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for (unsigned i = 0; i < LoopSize; i+=4) {
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unsigned scratch = MRI.createVirtualRegister(TRC);
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unsigned srcOut = MRI.createVirtualRegister(TRC);
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unsigned destOut = MRI.createVirtualRegister(TRC);
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if (isThumb2) {
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AddDefaultPred(BuildMI(*BB, MI, dl,
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TII->get(ldrOpc), scratch)
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.addReg(srcOut, RegState::Define).addReg(srcIn).addImm(4));
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AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
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.addReg(scratch).addReg(destIn)
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.addImm(4));
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} else {
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AddDefaultPred(BuildMI(*BB, MI, dl,
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TII->get(ldrOpc), scratch)
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.addReg(srcOut, RegState::Define).addReg(srcIn).addReg(0).addImm(4));
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AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
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.addReg(scratch).addReg(destIn)
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.addReg(0).addImm(4));
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}
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srcIn = srcOut;
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destIn = destOut;
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}
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// Handle the leftover bytes with LDRB and STRB.
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// [scratch, srcOut] = LDRB_POST(srcIn, 1)
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// [destOut] = STRB_POST(scratch, destIn, 1)
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ldrOpc = isThumb2 ? ARM::t2LDRB_POST : ARM::LDRB_POST_IMM;
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strOpc = isThumb2 ? ARM::t2STRB_POST : ARM::STRB_POST_IMM;
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for (unsigned i = 0; i < BytesLeft; i++) {
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unsigned scratch = MRI.createVirtualRegister(TRC);
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unsigned srcOut = MRI.createVirtualRegister(TRC);
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unsigned destOut = MRI.createVirtualRegister(TRC);
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if (isThumb2) {
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AddDefaultPred(BuildMI(*BB, MI, dl,
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TII->get(ldrOpc),scratch)
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.addReg(srcOut, RegState::Define).addReg(srcIn).addImm(1));
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AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
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.addReg(scratch).addReg(destIn)
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.addReg(0).addImm(1));
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} else {
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AddDefaultPred(BuildMI(*BB, MI, dl,
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TII->get(ldrOpc),scratch)
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.addReg(srcOut, RegState::Define).addReg(srcIn).addImm(1));
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AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
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.addReg(scratch).addReg(destIn)
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.addReg(0).addImm(1));
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}
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srcIn = srcOut;
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destIn = destOut;
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}
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MI->eraseFromParent(); // The instruction is gone now.
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return BB;
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}
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// Expand the pseudo op to a loop.
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// thisMBB:
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// ...
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// movw varEnd, # --> with thumb2
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// movt varEnd, #
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// ldrcp varEnd, idx --> without thumb2
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// fallthrough --> loopMBB
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// loopMBB:
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// PHI varPhi, varEnd, varLoop
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// PHI srcPhi, src, srcLoop
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// PHI destPhi, dst, destLoop
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// [scratch, srcLoop] = LDR_POST(srcPhi, 4)
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// [destLoop] = STR_POST(scratch, destPhi, 4)
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// subs varLoop, varPhi, #4
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// bne loopMBB
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// fallthrough --> exitMBB
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// exitMBB:
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// epilogue to handle left-over bytes
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// [scratch, srcOut] = LDRB_POST(srcLoop, 1)
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// [destOut] = STRB_POST(scratch, destLoop, 1)
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MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MF->insert(It, loopMBB);
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MF->insert(It, exitMBB);
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// Transfer the remainder of BB and its successor edges to exitMBB.
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exitMBB->splice(exitMBB->begin(), BB,
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llvm::next(MachineBasicBlock::iterator(MI)),
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BB->end());
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exitMBB->transferSuccessorsAndUpdatePHIs(BB);
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// Load an immediate to varEnd.
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unsigned varEnd = MRI.createVirtualRegister(TRC);
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if (isThumb2) {
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unsigned VReg1 = varEnd;
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if ((LoopSize & 0xFFFF0000) != 0)
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VReg1 = MRI.createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVi16), VReg1)
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.addImm(LoopSize & 0xFFFF));
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if ((LoopSize & 0xFFFF0000) != 0)
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AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVTi16), varEnd)
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.addReg(VReg1)
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.addImm(LoopSize >> 16));
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} else {
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MachineConstantPool *ConstantPool = MF->getConstantPool();
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Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
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const Constant *C = ConstantInt::get(Int32Ty, LoopSize);
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// MachineConstantPool wants an explicit alignment.
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unsigned Align = getTargetData()->getPrefTypeAlignment(Int32Ty);
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if (Align == 0)
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Align = getTargetData()->getTypeAllocSize(C->getType());
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unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
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AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::LDRcp))
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.addReg(varEnd, RegState::Define)
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.addConstantPoolIndex(Idx)
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.addImm(0));
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}
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BB->addSuccessor(loopMBB);
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// Generate the loop body:
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// varPhi = PHI(varLoop, varEnd)
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// srcPhi = PHI(srcLoop, src)
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// destPhi = PHI(destLoop, dst)
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MachineBasicBlock *entryBB = BB;
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BB = loopMBB;
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unsigned varLoop = MRI.createVirtualRegister(TRC);
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unsigned varPhi = MRI.createVirtualRegister(TRC);
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unsigned srcLoop = MRI.createVirtualRegister(TRC);
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unsigned srcPhi = MRI.createVirtualRegister(TRC);
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unsigned destLoop = MRI.createVirtualRegister(TRC);
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unsigned destPhi = MRI.createVirtualRegister(TRC);
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BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi)
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.addReg(varLoop).addMBB(loopMBB)
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.addReg(varEnd).addMBB(entryBB);
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BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi)
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.addReg(srcLoop).addMBB(loopMBB)
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.addReg(src).addMBB(entryBB);
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BuildMI(BB, dl, TII->get(ARM::PHI), destPhi)
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.addReg(destLoop).addMBB(loopMBB)
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.addReg(dest).addMBB(entryBB);
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// [scratch, srcLoop] = LDR_POST(srcPhi, 4)
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// [destLoop] = STR_POST(scratch, destPhi, 4)
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unsigned scratch = MRI.createVirtualRegister(TRC);
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if (isThumb2) {
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AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), scratch)
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.addReg(srcLoop, RegState::Define).addReg(srcPhi).addImm(4));
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AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), destLoop)
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.addReg(scratch).addReg(destPhi)
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.addImm(4));
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} else {
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AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), scratch)
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.addReg(srcLoop, RegState::Define).addReg(srcPhi).addReg(0).addImm(4));
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AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), destLoop)
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.addReg(scratch).addReg(destPhi)
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.addReg(0).addImm(4));
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}
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// Decrement loop variable by 4.
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MachineInstrBuilder MIB = BuildMI(BB, dl,
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TII->get(isThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop);
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AddDefaultCC(AddDefaultPred(MIB.addReg(varPhi).addImm(4)));
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MIB->getOperand(5).setReg(ARM::CPSR);
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MIB->getOperand(5).setIsDef(true);
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BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
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.addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
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// loopMBB can loop back to loopMBB or fall through to exitMBB.
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BB->addSuccessor(loopMBB);
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BB->addSuccessor(exitMBB);
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// Add epilogue to handle BytesLeft.
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BB = exitMBB;
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MachineInstr *StartOfExit = exitMBB->begin();
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ldrOpc = isThumb2 ? ARM::t2LDRB_POST : ARM::LDRB_POST_IMM;
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strOpc = isThumb2 ? ARM::t2STRB_POST : ARM::STRB_POST_IMM;
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// [scratch, srcOut] = LDRB_POST(srcLoop, 1)
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// [destOut] = STRB_POST(scratch, destLoop, 1)
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unsigned srcIn = srcLoop;
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unsigned destIn = destLoop;
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for (unsigned i = 0; i < BytesLeft; i++) {
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unsigned scratch = MRI.createVirtualRegister(TRC);
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unsigned srcOut = MRI.createVirtualRegister(TRC);
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unsigned destOut = MRI.createVirtualRegister(TRC);
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if (isThumb2) {
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AddDefaultPred(BuildMI(*BB, StartOfExit, dl,
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TII->get(ldrOpc),scratch)
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.addReg(srcOut, RegState::Define).addReg(srcIn).addImm(1));
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AddDefaultPred(BuildMI(*BB, StartOfExit, dl, TII->get(strOpc), destOut)
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.addReg(scratch).addReg(destIn)
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.addImm(1));
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} else {
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AddDefaultPred(BuildMI(*BB, StartOfExit, dl,
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TII->get(ldrOpc),scratch)
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.addReg(srcOut, RegState::Define).addReg(srcIn).addReg(0).addImm(1));
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AddDefaultPred(BuildMI(*BB, StartOfExit, dl, TII->get(strOpc), destOut)
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.addReg(scratch).addReg(destIn)
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.addReg(0).addImm(1));
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}
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srcIn = srcOut;
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destIn = destOut;
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}
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MI->eraseFromParent(); // The instruction is gone now.
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return BB;
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}
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}
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}
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@ -41,6 +41,9 @@ namespace llvm {
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// PIC mode.
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WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
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// Add pseudo op to model memcpy for struct byval.
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COPY_STRUCT_BYVAL,
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CALL, // Function call.
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CALL_PRED, // Function call that's predicable.
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CALL_NOLINK, // Function call with branch not branch-and-link.
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@ -18,6 +18,9 @@
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// Type profiles.
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def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
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def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
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def SDT_ARMStructByVal : SDTypeProfile<0, 3,
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[SDTCisVT<0, i32>, SDTCisVT<1, i32>,
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SDTCisVT<2, i32>]>;
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def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
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@ -90,6 +93,10 @@ def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
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[SDNPHasChain, SDNPOutGlue]>;
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def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
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def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
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SDT_ARMStructByVal,
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[SDNPHasChain, SDNPInGlue, SDNPOutGlue,
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SDNPMayStore, SDNPMayLoad]>;
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def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
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@ -4165,6 +4172,13 @@ let usesCustomInserter = 1 in {
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}
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}
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let usesCustomInserter = 1 in {
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def COPY_STRUCT_BYVAL_I32 : PseudoInst<
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(outs), (ins GPR:$dst, GPR:$src, i32imm:$size),
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NoItinerary,
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[(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size)]>;
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}
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let mayLoad = 1 in {
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def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
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NoItinerary,
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Block a user