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Some shl patterns which do load + store folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24689 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1017,17 +1017,27 @@ def SHL32ri : Ii8<0xC1, MRM4r, (ops R32:$dst, R32:$src1, i8imm:$src2),
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let isTwoAddress = 0 in {
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let isTwoAddress = 0 in {
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def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst),
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def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst),
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"shl{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
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"shl{b} {%cl, $dst|$dst, %CL}",
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[(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>,
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Imp<[CL],[]>;
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def SHL16mCL : I<0xD3, MRM4m, (ops i16mem:$dst),
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def SHL16mCL : I<0xD3, MRM4m, (ops i16mem:$dst),
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"shl{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
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"shl{w} {%cl, $dst|$dst, %CL}",
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[(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>,
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Imp<[CL],[]>, OpSize;
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def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst),
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def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst),
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"shl{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
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"shl{l} {%cl, $dst|$dst, %CL}",
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[(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>,
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Imp<[CL],[]>;
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def SHL8mi : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src),
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def SHL8mi : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src),
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"shl{b} {$src, $dst|$dst, $src}", []>;
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"shl{b} {$src, $dst|$dst, $src}",
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[(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
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def SHL16mi : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src),
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def SHL16mi : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src),
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"shl{w} {$src, $dst|$dst, $src}", []>, OpSize;
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"shl{w} {$src, $dst|$dst, $src}",
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[(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
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OpSize;
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def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src),
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def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src),
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"shl{l} {$src, $dst|$dst, $src}", []>;
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"shl{l} {$src, $dst|$dst, $src}",
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[(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
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}
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}
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def SHR8rCL : I<0xD2, MRM5r, (ops R8 :$dst, R8 :$src),
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def SHR8rCL : I<0xD2, MRM5r, (ops R8 :$dst, R8 :$src),
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