mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Refactor the bitcast code into its own function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55387 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -167,6 +167,9 @@ private:
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bool SelectGetElementPtr(Instruction *I,
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bool SelectGetElementPtr(Instruction *I,
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DenseMap<const Value*, unsigned> &ValueMap);
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DenseMap<const Value*, unsigned> &ValueMap);
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bool SelectBitCast(Instruction *I,
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DenseMap<const Value*, unsigned> &ValueMap);
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};
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};
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}
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}
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@@ -149,6 +149,72 @@ bool FastISel::SelectGetElementPtr(Instruction *I,
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return true;
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return true;
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}
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}
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bool FastISel::SelectBitCast(Instruction *I,
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DenseMap<const Value*, unsigned> &ValueMap) {
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// BitCast consists of either an immediate to register move
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// or a register to register move.
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if (ConstantInt* CI = dyn_cast<ConstantInt>(I->getOperand(0))) {
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if (I->getType()->isInteger()) {
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MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/false);
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unsigned result = FastEmit_i(VT.getSimpleVT(), VT.getSimpleVT(),
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ISD::Constant,
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CI->getZExtValue());
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if (!result)
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return false;
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ValueMap[I] = result;
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return true;
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}
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// TODO: Support vector and fp constants.
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return false;
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}
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if (!isa<Constant>(I->getOperand(0))) {
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// Bitcasts of non-constant values become reg-reg copies.
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MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
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MVT DstVT = MVT::getMVT(I->getType());
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if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
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DstVT == MVT::Other || !DstVT.isSimple() ||
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!TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
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// Unhandled type. Halt "fast" selection and bail.
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return false;
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unsigned Op0 = ValueMap[I->getOperand(0)];
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if (Op0 == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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// First, try to perform the bitcast by inserting a reg-reg copy.
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unsigned ResultReg = 0;
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if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
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TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
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TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
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ResultReg = createResultReg(DstClass);
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bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
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Op0, DstClass, SrcClass);
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if (!InsertedCopy)
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ResultReg = 0;
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}
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// If the reg-reg copy failed, select a BIT_CONVERT opcode.
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if (!ResultReg)
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ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
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ISD::BIT_CONVERT, Op0);
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if (!ResultReg)
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return false;
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ValueMap[I] = ResultReg;
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return true;
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}
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// TODO: Casting a non-integral constant?
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return false;
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}
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BasicBlock::iterator
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BasicBlock::iterator
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FastISel::SelectInstructions(BasicBlock::iterator Begin,
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FastISel::SelectInstructions(BasicBlock::iterator Begin,
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BasicBlock::iterator End,
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BasicBlock::iterator End,
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@@ -231,64 +297,8 @@ FastISel::SelectInstructions(BasicBlock::iterator Begin,
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break;
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break;
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case Instruction::BitCast:
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case Instruction::BitCast:
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// BitCast consists of either an immediate to register move
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if (!SelectBitCast(I, ValueMap)) return I;
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// or a register to register move.
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if (ConstantInt* CI = dyn_cast<ConstantInt>(I->getOperand(0))) {
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if (I->getType()->isInteger()) {
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MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/false);
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unsigned result = FastEmit_i(VT.getSimpleVT(), VT.getSimpleVT(),
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ISD::Constant,
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CI->getZExtValue());
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if (!result)
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return I;
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ValueMap[I] = result;
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break;
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break;
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} else
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// TODO: Support vector and fp constants.
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return I;
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} else if (!isa<Constant>(I->getOperand(0))) {
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// Bitcasts of non-constant values become reg-reg copies.
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MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
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MVT DstVT = MVT::getMVT(I->getType());
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if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
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DstVT == MVT::Other || !DstVT.isSimple() ||
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!TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
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// Unhandled type. Halt "fast" selection and bail.
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return I;
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unsigned Op0 = ValueMap[I->getOperand(0)];
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if (Op0 == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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// First, try to perform the bitcast by inserting a reg-reg copy.
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unsigned ResultReg = 0;
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if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
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TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
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TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
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ResultReg = createResultReg(DstClass);
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bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
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Op0, DstClass, SrcClass);
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if (!InsertedCopy)
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ResultReg = 0;
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}
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// If the reg-reg copy failed, select a BIT_CONVERT opcode.
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if (!ResultReg)
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ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
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ISD::BIT_CONVERT, Op0);
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if (!ResultReg)
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return I;
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ValueMap[I] = ResultReg;
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break;
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} else
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// TODO: Casting a non-integral constant?
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return I;
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case Instruction::FPToSI:
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case Instruction::FPToSI:
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if (!isa<ConstantFP>(I->getOperand(0))) {
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if (!isa<ConstantFP>(I->getOperand(0))) {
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@@ -348,6 +358,7 @@ FastISel::SelectInstructions(BasicBlock::iterator Begin,
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} else
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} else
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// TODO: Materialize constant and convert to FP.
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// TODO: Materialize constant and convert to FP.
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return I;
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return I;
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default:
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default:
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// Unhandled instruction. Halt "fast" selection and bail.
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// Unhandled instruction. Halt "fast" selection and bail.
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return I;
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return I;
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