mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
[Hexagon] Adding missing load instructions and removing an unused multiclass parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228630 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
a9a077681d
commit
76419c0533
@ -397,13 +397,27 @@ let accessSize = ByteAccess, hasNewValue = 1 in {
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let accessSize = HalfWordAccess, hasNewValue = 1 in {
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def L4_loadrh_ap : T_LD_abs_set <"memh", IntRegs, 0b1010>;
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def L4_loadruh_ap : T_LD_abs_set <"memuh", IntRegs, 0b1011>;
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def L4_loadbsw2_ap : T_LD_abs_set <"membh", IntRegs, 0b0001>;
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def L4_loadbzw2_ap : T_LD_abs_set <"memubh", IntRegs, 0b0011>;
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}
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let accessSize = WordAccess, hasNewValue = 1 in
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def L4_loadri_ap : T_LD_abs_set <"memw", IntRegs, 0b1100>;
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let accessSize = WordAccess in {
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def L4_loadbzw4_ap : T_LD_abs_set <"memubh", DoubleRegs, 0b0101>;
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def L4_loadbsw4_ap : T_LD_abs_set <"membh", DoubleRegs, 0b0111>;
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}
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let accessSize = DoubleWordAccess in
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def L4_loadrd_ap : T_LD_abs_set <"memd", DoubleRegs, 0b1110>;
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let accessSize = ByteAccess in
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def L4_loadalignb_ap : T_LD_abs_set <"memb_fifo", DoubleRegs, 0b0100>;
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let accessSize = HalfWordAccess in
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def L4_loadalignh_ap : T_LD_abs_set <"memh_fifo", DoubleRegs, 0b0010>;
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// Load - Indirect with long offset
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let InputType = "imm", addrMode = BaseLongOffset, isExtended = 1,
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opExtentBits = 6, opExtendable = 3 in
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@ -1327,6 +1341,31 @@ def L2_loadbsw2_pr : T_load_pr <"membh", IntRegs, 0b0001, HalfWordAccess>;
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def L2_loadbsw4_pr : T_load_pr <"membh", DoubleRegs, 0b0111, WordAccess>;
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let hasSideEffects = 0, addrMode = PostInc in
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class T_loadalign_pr <string mnemonic, bits<4> MajOp, MemAccessSize AccessSz>
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: LDInstPI <(outs DoubleRegs:$dst, IntRegs:$_dst_),
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(ins DoubleRegs:$src1, IntRegs:$src2, ModRegs:$src3),
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"$dst = "#mnemonic#"($src2++$src3)", [],
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"$src1 = $dst, $src2 = $_dst_"> {
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bits<5> dst;
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bits<5> src2;
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bits<1> src3;
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let accessSize = AccessSz;
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let IClass = 0b1001;
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let Inst{27-25} = 0b110;
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let Inst{24-21} = MajOp;
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let Inst{20-16} = src2;
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let Inst{13} = src3;
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let Inst{12} = 0b0;
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let Inst{7} = 0b0;
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let Inst{4-0} = dst;
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}
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def L2_loadalignb_pr : T_loadalign_pr <"memb_fifo", 0b0100, ByteAccess>;
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def L2_loadalignh_pr : T_loadalign_pr <"memh_fifo", 0b0010, HalfWordAccess>;
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//===----------------------------------------------------------------------===//
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// Template class for non-predicated post increment .new stores
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// mem[bhwd](Rx++#s4:[0123])=Nt.new
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@ -1738,6 +1777,26 @@ def C4_and_orn : T_LOGICAL_3OP<"and", "or", 0b01, 1>;
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def C4_or_andn : T_LOGICAL_3OP<"or", "and", 0b10, 1>;
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def C4_or_orn : T_LOGICAL_3OP<"or", "or", 0b11, 1>;
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// op(Ps, op(Pt, Pu))
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class LogLog_pat<SDNode Op1, SDNode Op2, InstHexagon MI>
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: Pat<(i1 (Op1 I1:$Ps, (Op2 I1:$Pt, I1:$Pu))),
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(MI I1:$Ps, I1:$Pt, I1:$Pu)>;
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// op(Ps, op(Pt, ~Pu))
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class LogLogNot_pat<SDNode Op1, SDNode Op2, InstHexagon MI>
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: Pat<(i1 (Op1 I1:$Ps, (Op2 I1:$Pt, (not I1:$Pu)))),
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(MI I1:$Ps, I1:$Pt, I1:$Pu)>;
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def: LogLog_pat<and, and, C4_and_and>;
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def: LogLog_pat<and, or, C4_and_or>;
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def: LogLog_pat<or, and, C4_or_and>;
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def: LogLog_pat<or, or, C4_or_or>;
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def: LogLogNot_pat<and, and, C4_and_andn>;
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def: LogLogNot_pat<and, or, C4_and_orn>;
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def: LogLogNot_pat<or, and, C4_or_andn>;
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def: LogLogNot_pat<or, or, C4_or_orn>;
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//===----------------------------------------------------------------------===//
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// CR -
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//===----------------------------------------------------------------------===//
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@ -2031,6 +2090,54 @@ def A4_bitsplit: ALU64Inst<(outs DoubleRegs:$Rd),
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let Inst{4-0} = Rd;
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}
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let hasSideEffects = 0 in
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def dep_S2_packhl: ALU64Inst<(outs DoubleRegs:$Rd),
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(ins IntRegs:$Rs, IntRegs:$Rt),
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"$Rd = packhl($Rs, $Rt):deprecated", [], "", ALU64_tc_1_SLOT23> {
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bits<5> Rd;
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bits<5> Rs;
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bits<5> Rt;
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let IClass = 0b1101;
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let Inst{27-24} = 0b0100;
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let Inst{21} = 0b0;
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let Inst{20-16} = Rs;
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let Inst{12-8} = Rt;
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let Inst{4-0} = Rd;
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}
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let hasNewValue = 1, hasSideEffects = 0 in
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def dep_A2_addsat: ALU64Inst<(outs IntRegs:$Rd),
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(ins IntRegs:$Rs, IntRegs:$Rt),
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"$Rd = add($Rs, $Rt):sat:deprecated", [], "", ALU64_tc_2_SLOT23> {
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bits<5> Rd;
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bits<5> Rs;
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bits<5> Rt;
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let IClass = 0b1101;
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let Inst{27-21} = 0b0101100;
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let Inst{20-16} = Rs;
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let Inst{12-8} = Rt;
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let Inst{7} = 0b0;
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let Inst{4-0} = Rd;
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}
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let hasNewValue = 1, hasSideEffects = 0 in
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def dep_A2_subsat: ALU64Inst<(outs IntRegs:$Rd),
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(ins IntRegs:$Rs, IntRegs:$Rt),
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"$Rd = sub($Rs, $Rt):sat:deprecated", [], "", ALU64_tc_2_SLOT23> {
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bits<5> Rd;
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bits<5> Rs;
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bits<5> Rt;
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let IClass = 0b1101;
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let Inst{27-21} = 0b0101100;
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let Inst{20-16} = Rt;
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let Inst{12-8} = Rs;
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let Inst{7} = 0b1;
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let Inst{4-0} = Rd;
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}
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// Rx[&|]=xor(Rs,Rt)
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def M4_or_xor : T_MType_acc_rr < "|= xor", 0b110, 0b001, 0>;
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def M4_and_xor : T_MType_acc_rr < "&= xor", 0b010, 0b010, 0>;
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@ -2054,6 +2161,24 @@ def M4_xor_andn : T_MType_acc_rr < "^= and", 0b001, 0b010, 0, [], 1>;
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def M4_or_andn : T_MType_acc_rr < "|= and", 0b001, 0b000, 0, [], 1>;
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def M4_and_andn : T_MType_acc_rr < "&= and", 0b001, 0b001, 0, [], 1>;
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def: T_MType_acc_pat2 <M4_or_xor, xor, or>;
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def: T_MType_acc_pat2 <M4_and_xor, xor, and>;
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def: T_MType_acc_pat2 <M4_or_and, and, or>;
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def: T_MType_acc_pat2 <M4_and_and, and, and>;
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def: T_MType_acc_pat2 <M4_xor_and, and, xor>;
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def: T_MType_acc_pat2 <M4_or_or, or, or>;
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def: T_MType_acc_pat2 <M4_and_or, or, and>;
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def: T_MType_acc_pat2 <M4_xor_or, or, xor>;
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class T_MType_acc_pat3 <InstHexagon MI, SDNode firstOp, SDNode secOp>
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: Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2,
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(not IntRegs:$src3)))),
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(i32 (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3))>;
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def: T_MType_acc_pat3 <M4_or_andn, and, or>;
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def: T_MType_acc_pat3 <M4_and_andn, and, and>;
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def: T_MType_acc_pat3 <M4_xor_andn, and, xor>;
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// Compound or-or and or-and
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let isExtentSigned = 1, InputType = "imm", hasNewValue = 1, isExtendable = 1,
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opExtentBits = 10, opExtendable = 3 in
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@ -2480,6 +2605,17 @@ defm S4_ori : T_ShiftOperate<"or", or, 0b01, ALU64_tc_1_SLOT23>;
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defm S4_subi : T_ShiftOperate<"sub", sub, 0b11, ALU64_tc_1_SLOT23>;
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let AddedComplexity = 200 in {
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def: Pat<(add addrga:$addr, (shl I32:$src2, u5ImmPred:$src3)),
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(S4_addi_asl_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
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def: Pat<(add addrga:$addr, (srl I32:$src2, u5ImmPred:$src3)),
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(S4_addi_lsr_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
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def: Pat<(sub addrga:$addr, (shl I32:$src2, u5ImmPred:$src3)),
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(S4_subi_asl_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
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def: Pat<(sub addrga:$addr, (srl I32:$src2, u5ImmPred:$src3)),
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(S4_subi_lsr_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
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}
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// Vector conditional negate
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// Rdd=vcnegh(Rss,Rt)
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let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in
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@ -2815,8 +2951,8 @@ let Predicates = [UseMEMOP] in {
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//===----------------------------------------------------------------------===//
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multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
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PatLeaf immPred, ComplexPattern addrPred,
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SDNodeXForm xformFunc, InstHexagon MI> {
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PatLeaf immPred, SDNodeXForm xformFunc,
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InstHexagon MI> {
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let AddedComplexity = 190 in
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def: Pat<(stOp (add (ldOp IntRegs:$addr), immPred:$subend), IntRegs:$addr),
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(MI IntRegs:$addr, 0, (xformFunc immPred:$subend))>;
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@ -2831,10 +2967,10 @@ multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
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multiclass MemOpi_m5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
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// Half Word
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defm: MemOpi_m5Pats <ldOpHalf, truncstorei16, u6_1ExtPred, m5HImmPred,
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ADDRriU6_1, MEMOPIMM_HALF, L4_isub_memoph_io>;
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MEMOPIMM_HALF, L4_isub_memoph_io>;
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// Byte
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defm: MemOpi_m5Pats <ldOpByte, truncstorei8, u6ExtPred, m5BImmPred,
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ADDRriU6_0, MEMOPIMM_BYTE, L4_isub_memopb_io>;
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MEMOPIMM_BYTE, L4_isub_memopb_io>;
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}
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let Predicates = [UseMEMOP] in {
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@ -2844,7 +2980,7 @@ let Predicates = [UseMEMOP] in {
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// Word
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defm: MemOpi_m5Pats <load, store, u6_2ExtPred, m5ImmPred,
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ADDRriU6_2, MEMOPIMM, L4_isub_memopw_io>;
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MEMOPIMM, L4_isub_memopw_io>;
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}
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//===----------------------------------------------------------------------===//
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@ -2854,8 +2990,8 @@ let Predicates = [UseMEMOP] in {
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//===----------------------------------------------------------------------===//
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multiclass MemOpi_bitPats <PatFrag ldOp, PatFrag stOp, PatLeaf immPred,
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PatLeaf extPred, ComplexPattern addrPred,
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SDNodeXForm xformFunc, InstHexagon MI, SDNode OpNode> {
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PatLeaf extPred, SDNodeXForm xformFunc, InstHexagon MI,
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SDNode OpNode> {
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// mem[bhw](Rs+#u6:[012]) = [clrbit|setbit](#U5)
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let AddedComplexity = 250 in
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@ -2866,25 +3002,23 @@ multiclass MemOpi_bitPats <PatFrag ldOp, PatFrag stOp, PatLeaf immPred,
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// mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
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let AddedComplexity = 225 in
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def: Pat<(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
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immPred:$bitend),
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(addrPred (i32 IntRegs:$addr), extPred:$offset)),
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(MI IntRegs:$addr, extPred:$offset, (xformFunc immPred:$bitend))>;
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def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), immPred:$bitend), IntRegs:$addr),
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(MI IntRegs:$addr, 0, (xformFunc immPred:$bitend))>;
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}
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multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
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multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf> {
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// Byte - clrbit
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defm: MemOpi_bitPats<ldOpByte, truncstorei8, Clr3ImmPred, u6ExtPred,
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ADDRriU6_0, CLRMEMIMM_BYTE, L4_iand_memopb_io, and>;
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CLRMEMIMM_BYTE, L4_iand_memopb_io, and>;
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// Byte - setbit
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defm: MemOpi_bitPats<ldOpByte, truncstorei8, Set3ImmPred, u6ExtPred,
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ADDRriU6_0, SETMEMIMM_BYTE, L4_ior_memopb_io, or>;
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defm: MemOpi_bitPats<ldOpByte, truncstorei8, Set3ImmPred, u6ExtPred,
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SETMEMIMM_BYTE, L4_ior_memopb_io, or>;
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// Half Word - clrbit
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defm: MemOpi_bitPats<ldOpHalf, truncstorei16, Clr4ImmPred, u6_1ExtPred,
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ADDRriU6_1, CLRMEMIMM_SHORT, L4_iand_memoph_io, and>;
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CLRMEMIMM_SHORT, L4_iand_memoph_io, and>;
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// Half Word - setbit
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defm: MemOpi_bitPats<ldOpHalf, truncstorei16, Set4ImmPred, u6_1ExtPred,
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ADDRriU6_1, SETMEMIMM_SHORT, L4_ior_memoph_io, or>;
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SETMEMIMM_SHORT, L4_ior_memoph_io, or>;
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}
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let Predicates = [UseMEMOP] in {
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@ -2896,10 +3030,10 @@ let Predicates = [UseMEMOP] in {
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// memw(Rs+#0) = [clrbit|setbit](#U5)
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// memw(Rs+#u6:2) = [clrbit|setbit](#U5)
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defm: MemOpi_bitPats<load, store, Clr5ImmPred, u6_2ExtPred, ADDRriU6_2,
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CLRMEMIMM, L4_iand_memopw_io, and>;
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defm: MemOpi_bitPats<load, store, Set5ImmPred, u6_2ExtPred, ADDRriU6_2,
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SETMEMIMM, L4_ior_memopw_io, or>;
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defm: MemOpi_bitPats<load, store, Clr5ImmPred, u6_2ExtPred, CLRMEMIMM,
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L4_iand_memopw_io, and>;
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defm: MemOpi_bitPats<load, store, Set5ImmPred, u6_2ExtPred, SETMEMIMM,
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L4_ior_memopw_io, or>;
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}
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//===----------------------------------------------------------------------===//
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@ -2909,14 +3043,13 @@ let Predicates = [UseMEMOP] in {
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// mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
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//===----------------------------------------------------------------------===//
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multiclass MemOpr_Pats <PatFrag ldOp, PatFrag stOp, ComplexPattern addrPred,
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PatLeaf extPred, InstHexagon MI, SDNode OpNode> {
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multiclass MemOpr_Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
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InstHexagon MI, SDNode OpNode> {
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let AddedComplexity = 141 in
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// mem[bhw](Rs+#0) [+-&|]= Rt
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def: Pat<(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
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(i32 IntRegs:$addend)),
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(addrPred (i32 IntRegs:$addr), extPred:$offset)),
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(MI IntRegs:$addr, extPred:$offset, (i32 IntRegs:$addend) )>;
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def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), (i32 IntRegs:$addend)),
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IntRegs:$addr),
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(MI IntRegs:$addr, 0, (i32 IntRegs:$addend))>;
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// mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
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let AddedComplexity = 150 in
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@ -2926,24 +3059,22 @@ multiclass MemOpr_Pats <PatFrag ldOp, PatFrag stOp, ComplexPattern addrPred,
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(MI IntRegs:$base, extPred:$offset, (i32 IntRegs:$orend))>;
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}
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multiclass MemOPr_ALUOp<PatFrag ldOp, PatFrag stOp,
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ComplexPattern addrPred, PatLeaf extPred,
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multiclass MemOPr_ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
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InstHexagon addMI, InstHexagon subMI,
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InstHexagon andMI, InstHexagon orMI > {
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defm: MemOpr_Pats <ldOp, stOp, addrPred, extPred, addMI, add>;
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defm: MemOpr_Pats <ldOp, stOp, addrPred, extPred, subMI, sub>;
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defm: MemOpr_Pats <ldOp, stOp, addrPred, extPred, andMI, and>;
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defm: MemOpr_Pats <ldOp, stOp, addrPred, extPred, orMI, or>;
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InstHexagon andMI, InstHexagon orMI> {
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defm: MemOpr_Pats <ldOp, stOp, extPred, addMI, add>;
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defm: MemOpr_Pats <ldOp, stOp, extPred, subMI, sub>;
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defm: MemOpr_Pats <ldOp, stOp, extPred, andMI, and>;
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defm: MemOpr_Pats <ldOp, stOp, extPred, orMI, or>;
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}
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multiclass MemOPr_ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
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// Half Word
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defm: MemOPr_ALUOp <ldOpHalf, truncstorei16, ADDRriU6_1, u6_1ExtPred,
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defm: MemOPr_ALUOp <ldOpHalf, truncstorei16, u6_1ExtPred,
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L4_add_memoph_io, L4_sub_memoph_io,
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L4_and_memoph_io, L4_or_memoph_io>;
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// Byte
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defm: MemOPr_ALUOp <ldOpByte, truncstorei8, ADDRriU6_0, u6ExtPred,
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defm: MemOPr_ALUOp <ldOpByte, truncstorei8, u6ExtPred,
|
||||
L4_add_memopb_io, L4_sub_memopb_io,
|
||||
L4_and_memopb_io, L4_or_memopb_io>;
|
||||
}
|
||||
@ -2955,7 +3086,7 @@ let Predicates = [UseMEMOP] in {
|
||||
defm: MemOPr_ExtType<sextloadi8, sextloadi16>; // sign extend
|
||||
defm: MemOPr_ExtType<extloadi8, extloadi16>; // any extend
|
||||
// Word
|
||||
defm: MemOPr_ALUOp <load, store, ADDRriU6_2, u6_2ExtPred, L4_add_memopw_io,
|
||||
defm: MemOPr_ALUOp <load, store, u6_2ExtPred, L4_add_memopw_io,
|
||||
L4_sub_memopw_io, L4_and_memopw_io, L4_or_memopw_io>;
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user