6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-09-30 19:55:11 +00:00
Code Issues Projects Releases Wiki Activity

Add support for the 'lane' modifier on vdup operands

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114030 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-09-15 22:13:23 +00:00
parent b9dadc9066
commit 765c4d9477
1 changed files with 25 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
View File

@ -53,6 +53,29 @@ static std::pair<unsigned, unsigned> GetDRegPair(unsigned QReg) {
}
}
static unsigned getDPRSuperRegForSPR(unsigned Reg) {
switch (Reg) {
default:
assert(0 && "Unexpected register enum");
case ARM::S0: case ARM::S1: return ARM::D0;
case ARM::S2: case ARM::S3: return ARM::D1;
case ARM::S4: case ARM::S5: return ARM::D2;
case ARM::S6: case ARM::S7: return ARM::D3;
case ARM::S8: case ARM::S9: return ARM::D4;
case ARM::S10: case ARM::S11: return ARM::D5;
case ARM::S12: case ARM::S13: return ARM::D6;
case ARM::S14: case ARM::S15: return ARM::D7;
case ARM::S16: case ARM::S17: return ARM::D8;
case ARM::S18: case ARM::S19: return ARM::D9;
case ARM::S20: case ARM::S21: return ARM::D10;
case ARM::S22: case ARM::S23: return ARM::D11;
case ARM::S24: case ARM::S25: return ARM::D12;
case ARM::S26: case ARM::S27: return ARM::D13;
case ARM::S28: case ARM::S29: return ARM::D14;
case ARM::S30: case ARM::S31: return ARM::D15;
}
}
void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
// Check for MOVs and print canonical forms, instead.
if (MI->getOpcode() == ARM::MOVs) {
@ -147,14 +170,9 @@ void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
O << '{' << getRegisterName(dregpair.first) << ", "
<< getRegisterName(dregpair.second) << '}';
} else if (Modifier && strcmp(Modifier, "lane") == 0) {
// FIXME
assert(0);
/*
unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
&ARM::DPR_VFP2RegClass);
unsigned RegNum = getARMRegisterNumbering(Reg);
unsigned DReg = getDPRSuperRegForSPR(Reg);
O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
*/
} else {
O << getRegisterName(Reg);
}