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Fix warnings.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78725 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2009-08-11 21:59:30 +00:00
parent a1a1f02708
commit 766b5efd99
4 changed files with 13 additions and 15 deletions
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6
include/llvm/CodeGen/ValueTypes.h
View File

@ -334,9 +334,9 @@ namespace llvm {
const Type *LLVMTy;
public:
EVT() : V((MVT::SimpleValueType)(MVT::LastSimpleValueType+1)) {}
EVT(MVT::SimpleValueType SVT) : V(SVT) { }
EVT(MVT S) : V(S) {}
EVT() : V((MVT::SimpleValueType)(MVT::LastSimpleValueType+1)), LLVMTy(0) {}
EVT(MVT::SimpleValueType SVT) : V(SVT), LLVMTy(0) { }
EVT(MVT S) : V(S), LLVMTy(0) {}
bool operator==(const EVT VT) const {
if (V.SimpleTy == VT.V.SimpleTy) {

8
lib/CodeGen/SelectionDAG/FastISel.cpp
View File

@ -174,14 +174,12 @@ unsigned FastISel::getRegForGEPIndex(Value *Idx) {
return 0;
// If the index is smaller or larger than intptr_t, truncate or extend it.
EVT PtrVT = TLI.getPointerTy();
MVT PtrVT = TLI.getPointerTy();
EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
if (IdxVT.bitsLT(PtrVT))
IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
ISD::SIGN_EXTEND, IdxN);
IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN);
else if (IdxVT.bitsGT(PtrVT))
IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
ISD::TRUNCATE, IdxN);
IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN);
return IdxN;
}

8
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -1357,7 +1357,7 @@ SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) {
/// the target's desired shift amount type.
SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) {
EVT OpTy = Op.getValueType();
EVT ShTy = TLI.getShiftAmountTy();
MVT ShTy = TLI.getShiftAmountTy();
if (OpTy == ShTy || OpTy.isVector()) return Op;
ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
@ -3042,7 +3042,7 @@ static SDValue getMemsetStringVal(EVT VT, DebugLoc dl, SelectionDAG &DAG,
if (VT.isInteger())
return DAG.getConstant(0, VT);
unsigned NumElts = VT.getVectorNumElements();
EVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
DAG.getConstant(0, EVT::getVectorVT(EltVT, NumElts)));
}
@ -3144,9 +3144,9 @@ bool MeetsMaxMemopRequirement(std::vector<EVT> &MemOps,
}
}
EVT LVT = MVT::i64;
MVT LVT = MVT::i64;
while (!TLI.isTypeLegal(LVT))
LVT = (MVT::SimpleValueType)(LVT.getSimpleVT().SimpleTy - 1);
LVT = (MVT::SimpleValueType)(LVT.SimpleTy - 1);
assert(LVT.isInteger());
if (VT.bitsGT(LVT))

6
lib/Target/X86/X86ISelLowering.cpp
View File

@ -3889,11 +3889,11 @@ static SDValue getVZextMovL(EVT VT, EVT OpVT,
if (!LD) {
// movssrr and movsdrr do not clear top bits. Try to use movd, movq
// instead.
EVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
if ((EVT != MVT::i64 || Subtarget->is64Bit()) &&
MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
// PR2108
OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
return DAG.getNode(ISD::BIT_CONVERT, dl, VT,