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Add missing operand. <rdar://problem/10313323>

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142615 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2011-10-20 20:37:11 +00:00
parent 19595dc4d0
commit 767f8be9ee
1 changed files with 2 additions and 1 deletions
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3
lib/Target/ARM/ARMISelLowering.cpp
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@ -5924,7 +5924,8 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
unsigned VReg1 = MRI->createVirtualRegister(TRC);
AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
.addReg(VReg1, RegState::Define)
.addConstantPoolIndex(Idx));
.addConstantPoolIndex(Idx)
.addImm(0));
AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
.addReg(NewVReg1)
.addReg(VReg1, RegState::Kill));