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Add a const qualifier.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83677 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
2009-10-09 22:09:05 +00:00
parent bdb984bc27
commit 769b7f8953
2 changed files with 3 additions and 3 deletions
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2
include/llvm/Target/TargetRegisterInfo.h
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@@ -325,7 +325,7 @@ public:
/// getAllocatableSet - Returns a bitset indexed by register number /// getAllocatableSet - Returns a bitset indexed by register number
/// indicating if a register is allocatable or not. If a register class is /// indicating if a register is allocatable or not. If a register class is
/// specified, returns the subset for the class. /// specified, returns the subset for the class.
BitVector getAllocatableSet(MachineFunction &MF, BitVector getAllocatableSet(const MachineFunction &MF,
const TargetRegisterClass *RC = NULL) const; const TargetRegisterClass *RC = NULL) const;
const TargetRegisterDesc &operator[](unsigned RegNo) const { const TargetRegisterDesc &operator[](unsigned RegNo) const {

4
lib/Target/TargetRegisterInfo.cpp
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@@ -62,14 +62,14 @@ TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, EVT VT) const {
/// getAllocatableSetForRC - Toggle the bits that represent allocatable /// getAllocatableSetForRC - Toggle the bits that represent allocatable
/// registers for the specific register class. /// registers for the specific register class.
static void getAllocatableSetForRC(MachineFunction &MF, static void getAllocatableSetForRC(const MachineFunction &MF,
const TargetRegisterClass *RC, BitVector &R){ const TargetRegisterClass *RC, BitVector &R){
for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
E = RC->allocation_order_end(MF); I != E; ++I) E = RC->allocation_order_end(MF); I != E; ++I)
R.set(*I); R.set(*I);
} }
BitVector TargetRegisterInfo::getAllocatableSet(MachineFunction &MF, BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
const TargetRegisterClass *RC) const { const TargetRegisterClass *RC) const {
BitVector Allocatable(NumRegs); BitVector Allocatable(NumRegs);
if (RC) { if (RC) {