From 76acc872b3c63c26a83c2832ece6fa9b04786f24 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sun, 18 Dec 2005 02:37:35 +0000 Subject: [PATCH] Add constant pool support, including folding into addresses. Pretty print addresses a bit, to not print [%r1+%g0]: just print [%r1] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24813 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Sparc/SparcAsmPrinter.cpp | 14 +++++++++++++- lib/Target/Sparc/SparcISelDAGToDAG.cpp | 8 ++++++++ lib/Target/Sparc/SparcInstrInfo.td | 4 +++- lib/Target/SparcV8/SparcV8AsmPrinter.cpp | 14 +++++++++++++- lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp | 8 ++++++++ lib/Target/SparcV8/SparcV8InstrInfo.td | 4 +++- 6 files changed, 48 insertions(+), 4 deletions(-) diff --git a/lib/Target/Sparc/SparcAsmPrinter.cpp b/lib/Target/Sparc/SparcAsmPrinter.cpp index ea4971c995e..f64bd7eddaf 100644 --- a/lib/Target/Sparc/SparcAsmPrinter.cpp +++ b/lib/Target/Sparc/SparcAsmPrinter.cpp @@ -185,8 +185,20 @@ void SparcV8AsmPrinter::printOperand(const MachineInstr *MI, int opNum) { void SparcV8AsmPrinter::printMemOperand(const MachineInstr *MI, int opNum) { printOperand(MI, opNum); + MachineOperand::MachineOperandType OpTy = MI->getOperand(opNum+1).getType(); + + if ((OpTy == MachineOperand::MO_VirtualRegister || + OpTy == MachineOperand::MO_MachineRegister) && + MI->getOperand(opNum+1).getReg() == V8::G0) + return; // don't print "+%g0" + if ((OpTy == MachineOperand::MO_SignExtendedImmed || + OpTy == MachineOperand::MO_UnextendedImmed) && + MI->getOperand(opNum+1).getImmedValue() == 0) + return; // don't print "+0" + O << "+"; - if (MI->getOperand(opNum+1).getType() == MachineOperand::MO_GlobalAddress) { + if (OpTy == MachineOperand::MO_GlobalAddress || + OpTy == MachineOperand::MO_ConstantPoolIndex) { O << "%lo("; printOperand(MI, opNum+1); O << ")"; diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index aa558d189cb..860c76fdb14 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -75,6 +75,7 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM) // Custom legalize GlobalAddress nodes into LO/HI parts. setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); + setOperationAction(ISD::ConstantPool , MVT::i32, Custom); // Sparc doesn't have sext_inreg, replace them with shl/sra setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand); @@ -251,6 +252,13 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) { SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA); return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); } + case ISD::ConstantPool: { + Constant *C = cast(Op)->get(); + SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32); + SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP); + SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP); + return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); + } } } diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index eaa6691fee3..22ed2417df5 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -660,6 +660,8 @@ def : Pat<(i32 simm13:$val), def : Pat<(i32 imm:$val), (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; -// Global addresses +// Global addresses, constant pool entries def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>; +def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>; +def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>; diff --git a/lib/Target/SparcV8/SparcV8AsmPrinter.cpp b/lib/Target/SparcV8/SparcV8AsmPrinter.cpp index ea4971c995e..f64bd7eddaf 100644 --- a/lib/Target/SparcV8/SparcV8AsmPrinter.cpp +++ b/lib/Target/SparcV8/SparcV8AsmPrinter.cpp @@ -185,8 +185,20 @@ void SparcV8AsmPrinter::printOperand(const MachineInstr *MI, int opNum) { void SparcV8AsmPrinter::printMemOperand(const MachineInstr *MI, int opNum) { printOperand(MI, opNum); + MachineOperand::MachineOperandType OpTy = MI->getOperand(opNum+1).getType(); + + if ((OpTy == MachineOperand::MO_VirtualRegister || + OpTy == MachineOperand::MO_MachineRegister) && + MI->getOperand(opNum+1).getReg() == V8::G0) + return; // don't print "+%g0" + if ((OpTy == MachineOperand::MO_SignExtendedImmed || + OpTy == MachineOperand::MO_UnextendedImmed) && + MI->getOperand(opNum+1).getImmedValue() == 0) + return; // don't print "+0" + O << "+"; - if (MI->getOperand(opNum+1).getType() == MachineOperand::MO_GlobalAddress) { + if (OpTy == MachineOperand::MO_GlobalAddress || + OpTy == MachineOperand::MO_ConstantPoolIndex) { O << "%lo("; printOperand(MI, opNum+1); O << ")"; diff --git a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp index aa558d189cb..860c76fdb14 100644 --- a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp +++ b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp @@ -75,6 +75,7 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM) // Custom legalize GlobalAddress nodes into LO/HI parts. setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); + setOperationAction(ISD::ConstantPool , MVT::i32, Custom); // Sparc doesn't have sext_inreg, replace them with shl/sra setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand); @@ -251,6 +252,13 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) { SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA); return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); } + case ISD::ConstantPool: { + Constant *C = cast(Op)->get(); + SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32); + SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP); + SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP); + return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); + } } } diff --git a/lib/Target/SparcV8/SparcV8InstrInfo.td b/lib/Target/SparcV8/SparcV8InstrInfo.td index eaa6691fee3..22ed2417df5 100644 --- a/lib/Target/SparcV8/SparcV8InstrInfo.td +++ b/lib/Target/SparcV8/SparcV8InstrInfo.td @@ -660,6 +660,8 @@ def : Pat<(i32 simm13:$val), def : Pat<(i32 imm:$val), (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; -// Global addresses +// Global addresses, constant pool entries def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>; +def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>; +def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;