mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-12 17:32:19 +00:00
Keep track of the last place a live virtreg was used.
This allows us to add accurate kill markers, something the scavenger likes. Add some more tests from ARM that needed this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103521 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
9d7019f586
commit
76b4d5a021
@ -56,9 +56,22 @@ namespace {
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// values are spilled.
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IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
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// Virt2PhysMap - This map contains entries for each virtual register
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// Everything we know about a live virtual register.
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struct LiveReg {
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MachineInstr *LastUse; // Last instr to use reg.
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unsigned PhysReg; // Currently held here.
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unsigned LastOpNum; // OpNum on LastUse.
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LiveReg(unsigned p=0) : LastUse(0), PhysReg(p), LastOpNum(0) {
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assert(p && "Don't create LiveRegs without a PhysReg");
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}
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};
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typedef DenseMap<unsigned, LiveReg> LiveRegMap;
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// LiveVirtRegs - This map contains entries for each virtual register
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// that is currently available in a physical register.
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DenseMap<unsigned, unsigned> Virt2PhysMap;
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LiveRegMap LiveVirtRegs;
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// RegState - Track the state of a physical register.
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enum RegState {
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@ -77,7 +90,7 @@ namespace {
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// A register state may also be a virtual register number, indication that
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// the physical register is currently allocated to a virtual register. In
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// that case, Virt2PhysMap contains the inverse mapping.
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// that case, LiveVirtRegs contains the inverse mapping.
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};
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// PhysRegState - One of the RegState enums, or a virtreg.
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@ -112,18 +125,20 @@ namespace {
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void AllocateBasicBlock(MachineBasicBlock &MBB);
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int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
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void killVirtReg(unsigned VirtReg);
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void killVirtReg(LiveRegMap::iterator i);
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void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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unsigned VirtReg, bool isKill);
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void killPhysReg(unsigned PhysReg);
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void spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
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unsigned PhysReg, bool isKill);
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void assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg);
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unsigned allocVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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unsigned VirtReg);
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LiveRegMap::iterator assignVirtToPhysReg(unsigned VirtReg,
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unsigned PhysReg);
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LiveRegMap::iterator allocVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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unsigned VirtReg);
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unsigned defineVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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unsigned VirtReg);
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unsigned OpNum, unsigned VirtReg);
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unsigned reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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unsigned VirtReg);
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unsigned OpNum, unsigned VirtReg);
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void reservePhysReg(MachineBasicBlock &MBB, MachineInstr *MI,
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unsigned PhysReg);
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void spillAll(MachineBasicBlock &MBB, MachineInstr *MI);
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@ -149,55 +164,79 @@ int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
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return FrameIdx;
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}
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/// killVirtReg - Mark virtreg as no longer available.
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void RAFast::killVirtReg(LiveRegMap::iterator i) {
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assert(i != LiveVirtRegs.end() && "Killing unmapped virtual register");
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unsigned VirtReg = i->first;
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const LiveReg &LR = i->second;
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assert(PhysRegState[LR.PhysReg] == VirtReg && "Broken RegState mapping");
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PhysRegState[LR.PhysReg] = regFree;
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if (LR.LastUse) {
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MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
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if (MO.isUse()) MO.setIsKill();
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else MO.setIsDead();
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DEBUG(dbgs() << " - last seen here: " << *LR.LastUse);
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}
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LiveVirtRegs.erase(i);
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}
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/// killVirtReg - Mark virtreg as no longer available.
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void RAFast::killVirtReg(unsigned VirtReg) {
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"killVirtReg needs a virtual register");
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DEBUG(dbgs() << " Killing %reg" << VirtReg << "\n");
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DenseMap<unsigned,unsigned>::iterator i = Virt2PhysMap.find(VirtReg);
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if (i == Virt2PhysMap.end()) return;
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unsigned PhysReg = i->second;
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assert(PhysRegState[PhysReg] == VirtReg && "Broken RegState mapping");
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PhysRegState[PhysReg] = regFree;
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Virt2PhysMap.erase(i);
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LiveRegMap::iterator i = LiveVirtRegs.find(VirtReg);
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if (i != LiveVirtRegs.end())
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killVirtReg(i);
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}
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/// spillVirtReg - This method spills the value specified by VirtReg into the
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/// corresponding stack slot if needed. If isKill is set, the register is also
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/// killed.
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void RAFast::spillVirtReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator MI,
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unsigned VirtReg, bool isKill) {
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"Spilling a physical register is illegal!");
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DenseMap<unsigned,unsigned>::iterator i = Virt2PhysMap.find(VirtReg);
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assert(i != Virt2PhysMap.end() && "Spilling unmapped virtual register");
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unsigned PhysReg = i->second;
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assert(PhysRegState[PhysReg] == VirtReg && "Broken RegState mapping");
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LiveRegMap::iterator i = LiveVirtRegs.find(VirtReg);
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assert(i != LiveVirtRegs.end() && "Spilling unmapped virtual register");
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const LiveReg &LR = i->second;
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assert(PhysRegState[LR.PhysReg] == VirtReg && "Broken RegState mapping");
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if (PhysRegDirty.test(PhysReg)) {
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PhysRegDirty.reset(PhysReg);
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DEBUG(dbgs() << " Spilling register " << TRI->getName(PhysReg)
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// If this physreg is used by the instruction, we want to kill it on the
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// instruction, not on the spill.
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bool spillKill = isKill && LR.LastUse != MI;
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if (PhysRegDirty.test(LR.PhysReg)) {
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PhysRegDirty.reset(LR.PhysReg);
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DEBUG(dbgs() << " Spilling register " << TRI->getName(LR.PhysReg)
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<< " containing %reg" << VirtReg);
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const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
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int FrameIndex = getStackSpaceFor(VirtReg, RC);
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DEBUG(dbgs() << " to stack slot #" << FrameIndex << "\n");
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TII->storeRegToStackSlot(MBB, I, PhysReg, isKill, FrameIndex, RC, TRI);
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TII->storeRegToStackSlot(MBB, MI, LR.PhysReg, spillKill,
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FrameIndex, RC, TRI);
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++NumStores; // Update statistics
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if (spillKill)
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i->second.LastUse = 0; // Don't kill register again
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else if (!isKill) {
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MachineInstr *Spill = llvm::prior(MI);
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i->second.LastUse = Spill;
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i->second.LastOpNum = Spill->findRegisterUseOperandIdx(LR.PhysReg);
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}
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}
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if (isKill) {
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PhysRegState[PhysReg] = regFree;
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Virt2PhysMap.erase(i);
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}
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if (isKill)
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killVirtReg(i);
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}
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/// spillAll - Spill all dirty virtregs without killing them.
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void RAFast::spillAll(MachineBasicBlock &MBB, MachineInstr *MI) {
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SmallVector<unsigned, 16> Dirty;
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for (DenseMap<unsigned,unsigned>::iterator i = Virt2PhysMap.begin(),
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e = Virt2PhysMap.end(); i != e; ++i)
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if (PhysRegDirty.test(i->second))
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for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
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e = LiveVirtRegs.end(); i != e; ++i)
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if (PhysRegDirty.test(i->second.PhysReg))
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Dirty.push_back(i->first);
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for (unsigned i = 0, e = Dirty.size(); i != e; ++i)
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spillVirtReg(MBB, MI, Dirty[i], false);
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@ -276,16 +315,18 @@ void RAFast::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *MI,
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/// that PhysReg is the proper container for VirtReg now. The physical
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/// register must not be used for anything else when this is called.
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///
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void RAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
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RAFast::LiveRegMap::iterator
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RAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
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DEBUG(dbgs() << " Assigning %reg" << VirtReg << " to "
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<< TRI->getName(PhysReg) << "\n");
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Virt2PhysMap.insert(std::make_pair(VirtReg, PhysReg));
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PhysRegState[PhysReg] = VirtReg;
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return LiveVirtRegs.insert(std::make_pair(VirtReg, PhysReg)).first;
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}
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/// allocVirtReg - Allocate a physical register for VirtReg.
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unsigned RAFast::allocVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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unsigned VirtReg) {
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RAFast::LiveRegMap::iterator RAFast::allocVirtReg(MachineBasicBlock &MBB,
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MachineInstr *MI,
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unsigned VirtReg) {
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const unsigned spillCost = 100;
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"Can only allocate virtual registers");
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@ -305,10 +346,8 @@ unsigned RAFast::allocVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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case regReserved:
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continue;
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case regFree:
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if (!UsedInInstr.test(PhysReg)) {
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assignVirtToPhysReg(VirtReg, PhysReg);
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return PhysReg;
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}
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if (!UsedInInstr.test(PhysReg))
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return assignVirtToPhysReg(VirtReg, PhysReg);
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continue;
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default:
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// Grab the first spillable register we meet.
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@ -387,8 +426,7 @@ unsigned RAFast::allocVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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}
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}
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}
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assignVirtToPhysReg(VirtReg, BestReg);
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return BestReg;
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return assignVirtToPhysReg(VirtReg, BestReg);
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}
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// Nothing we can do.
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@ -401,40 +439,44 @@ unsigned RAFast::allocVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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MI->print(Msg, TM);
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}
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report_fatal_error(Msg.str());
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return 0;
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return LiveVirtRegs.end();
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}
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/// defineVirtReg - Allocate a register for VirtReg and mark it as dirty.
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unsigned RAFast::defineVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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unsigned VirtReg) {
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unsigned OpNum, unsigned VirtReg) {
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"Not a virtual register");
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unsigned PhysReg = Virt2PhysMap.lookup(VirtReg);
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if (!PhysReg)
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PhysReg = allocVirtReg(MBB, MI, VirtReg);
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UsedInInstr.set(PhysReg);
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PhysRegDirty.set(PhysReg);
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return PhysReg;
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LiveRegMap::iterator i = LiveVirtRegs.find(VirtReg);
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if (i == LiveVirtRegs.end())
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i = allocVirtReg(MBB, MI, VirtReg);
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i->second.LastUse = MI;
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i->second.LastOpNum = OpNum;
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UsedInInstr.set(i->second.PhysReg);
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PhysRegDirty.set(i->second.PhysReg);
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return i->second.PhysReg;
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}
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/// reloadVirtReg - Make sure VirtReg is available in a physreg and return it.
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unsigned RAFast::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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unsigned VirtReg) {
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unsigned OpNum, unsigned VirtReg) {
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"Not a virtual register");
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unsigned PhysReg = Virt2PhysMap.lookup(VirtReg);
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if (!PhysReg) {
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PhysReg = allocVirtReg(MBB, MI, VirtReg);
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PhysRegDirty.reset(PhysReg);
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LiveRegMap::iterator i = LiveVirtRegs.find(VirtReg);
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if (i == LiveVirtRegs.end()) {
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i = allocVirtReg(MBB, MI, VirtReg);
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PhysRegDirty.reset(i->second.PhysReg);
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const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
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int FrameIndex = getStackSpaceFor(VirtReg, RC);
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DEBUG(dbgs() << " Reloading %reg" << VirtReg << " into "
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<< TRI->getName(PhysReg) << "\n");
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TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC, TRI);
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<< TRI->getName(i->second.PhysReg) << "\n");
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TII->loadRegFromStackSlot(MBB, MI, i->second.PhysReg, FrameIndex, RC, TRI);
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++NumLoads;
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}
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UsedInInstr.set(PhysReg);
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return PhysReg;
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i->second.LastUse = MI;
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i->second.LastOpNum = OpNum;
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UsedInInstr.set(i->second.PhysReg);
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return i->second.PhysReg;
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}
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/// reservePhysReg - Mark PhysReg as reserved. This is very similar to
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@ -491,7 +533,7 @@ void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
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DEBUG(dbgs() << "\nBB#" << MBB.getNumber() << ", "<< MBB.getName() << "\n");
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PhysRegState.assign(TRI->getNumRegs(), regDisabled);
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assert(Virt2PhysMap.empty() && "Mapping not cleared form last block?");
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assert(LiveVirtRegs.empty() && "Mapping not cleared form last block?");
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PhysRegDirty.reset();
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MachineBasicBlock::iterator MII = MBB.begin();
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@ -522,20 +564,21 @@ void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
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dbgs() << "=%reg" << PhysRegState[Reg];
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if (PhysRegDirty.test(Reg))
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dbgs() << "*";
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assert(Virt2PhysMap.lookup(PhysRegState[Reg]) == Reg &&
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assert(LiveVirtRegs[PhysRegState[Reg]].PhysReg == Reg &&
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"Bad inverse map");
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break;
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}
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}
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dbgs() << '\n';
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// Check that Virt2PhysMap is the inverse.
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for (DenseMap<unsigned,unsigned>::iterator i = Virt2PhysMap.begin(),
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e = Virt2PhysMap.end(); i != e; ++i) {
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// Check that LiveVirtRegs is the inverse.
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for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
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e = LiveVirtRegs.end(); i != e; ++i) {
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assert(TargetRegisterInfo::isVirtualRegister(i->first) &&
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"Bad map key");
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assert(TargetRegisterInfo::isPhysicalRegister(i->second) &&
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assert(TargetRegisterInfo::isPhysicalRegister(i->second.PhysReg) &&
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"Bad map value");
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assert(PhysRegState[i->second] == i->first && "Bad inverse map");
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assert(PhysRegState[i->second.PhysReg] == i->first &&
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"Bad inverse map");
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}
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});
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@ -546,8 +589,11 @@ void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
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// This may be 0 if the register is currently spilled. Tough.
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setPhysReg(MO, Virt2PhysMap.lookup(Reg));
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LiveRegMap::iterator i = LiveVirtRegs.find(Reg);
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if (i != LiveVirtRegs.end())
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setPhysReg(MO, i->second.PhysReg);
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else
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MO.setReg(0); // We can't allocate a physreg for a DebugValue, sorry!
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}
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// Next instruction.
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continue;
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@ -589,11 +635,11 @@ void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
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unsigned Reg = MO.getReg();
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if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
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if (MO.isUse()) {
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setPhysReg(MO, reloadVirtReg(MBB, MI, Reg));
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setPhysReg(MO, reloadVirtReg(MBB, MI, i, Reg));
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if (MO.isKill())
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VirtKills.push_back(Reg);
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} else if (MO.isEarlyClobber()) {
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unsigned PhysReg = defineVirtReg(MBB, MI, Reg);
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unsigned PhysReg = defineVirtReg(MBB, MI, i, Reg);
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setPhysReg(MO, PhysReg);
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PhysDefs.push_back(PhysReg);
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}
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@ -640,7 +686,7 @@ void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
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}
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if (MO.isDead())
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VirtKills.push_back(Reg);
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setPhysReg(MO, defineVirtReg(MBB, MI, Reg));
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setPhysReg(MO, defineVirtReg(MBB, MI, i, Reg));
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}
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// Spill all dirty virtregs before a call, in case of an exception.
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@ -665,8 +711,8 @@ void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
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// Spill all physical registers holding virtual registers now.
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DEBUG(dbgs() << "Killing live registers at end of block.\n");
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MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
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while (!Virt2PhysMap.empty())
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spillVirtReg(MBB, MI, Virt2PhysMap.begin()->first, true);
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while (!LiveVirtRegs.empty())
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spillVirtReg(MBB, MI, LiveVirtRegs.begin()->first, true);
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DEBUG(MBB.dump());
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}
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@ -1,4 +1,5 @@
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; RUN: llc < %s -mtriple=arm-linux-gnueabi -regalloc=local
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; RUN: llc < %s -mtriple=arm-linux-gnueabi -regalloc=fast
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; PR1925
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%struct.encode_aux_nearestmatch = type { i32*, i32*, i32*, i32*, i32, i32 }
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@ -1,4 +1,5 @@
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; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=local
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; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=fast
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; PR1925
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%"struct.kc::impl_Ccode_option" = type { %"struct.kc::impl_abstract_phylum" }
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@ -1,4 +1,5 @@
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; RUN: llc < %s -mtriple=armv5-unknown-linux-gnueabi -O0 -regalloc=local
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; RUN: llc < %s -mtriple=armv5-unknown-linux-gnueabi -O0 -regalloc=fast
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; PR4100
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@.str = external constant [30 x i8] ; <[30 x i8]*> [#uses=1]
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