mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-01 10:57:21 +00:00
[X86] Merge a switch statement inside a default case of another switch statement on the same variable. There was no additional code in the default so this should be no functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225345 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
ebddeaee40
commit
76bdb26595
@ -2267,6 +2267,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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unsigned MIOpc = MI->getOpcode();
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switch (MIOpc) {
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default: return nullptr;
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case X86::SHL64ri: {
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assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
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unsigned ShAmt = getTruncatedShiftCount(MI, 2);
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@ -2321,181 +2322,175 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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.addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
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break;
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}
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default: {
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case X86::INC64r:
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case X86::INC32r: {
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assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
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unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
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: (is64Bit ? X86::LEA64_32r : X86::LEA32r);
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bool isKill, isUndef;
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unsigned SrcReg;
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MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
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if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
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SrcReg, isKill, isUndef, ImplicitOp))
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return nullptr;
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switch (MIOpc) {
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default: return nullptr;
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case X86::INC64r:
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case X86::INC32r: {
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assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
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unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
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: (is64Bit ? X86::LEA64_32r : X86::LEA32r);
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bool isKill, isUndef;
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unsigned SrcReg;
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MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
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if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
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SrcReg, isKill, isUndef, ImplicitOp))
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return nullptr;
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MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
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.addOperand(Dest)
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.addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
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if (ImplicitOp.getReg() != 0)
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MIB.addOperand(ImplicitOp);
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MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
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.addOperand(Dest)
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.addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
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if (ImplicitOp.getReg() != 0)
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MIB.addOperand(ImplicitOp);
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NewMI = addOffset(MIB, 1);
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break;
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}
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case X86::INC16r:
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if (DisableLEA16)
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return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
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: nullptr;
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assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
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NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
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.addOperand(Dest).addOperand(Src), 1);
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break;
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case X86::DEC64r:
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case X86::DEC32r: {
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assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
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unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
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: (is64Bit ? X86::LEA64_32r : X86::LEA32r);
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bool isKill, isUndef;
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unsigned SrcReg;
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MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
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if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
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SrcReg, isKill, isUndef, ImplicitOp))
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return nullptr;
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MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
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.addOperand(Dest)
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.addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
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if (ImplicitOp.getReg() != 0)
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MIB.addOperand(ImplicitOp);
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NewMI = addOffset(MIB, -1);
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break;
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}
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case X86::DEC16r:
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if (DisableLEA16)
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return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
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: nullptr;
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assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
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NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
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.addOperand(Dest).addOperand(Src), -1);
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break;
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case X86::ADD64rr:
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case X86::ADD64rr_DB:
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case X86::ADD32rr:
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case X86::ADD32rr_DB: {
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assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
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unsigned Opc;
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if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
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Opc = X86::LEA64r;
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else
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Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
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bool isKill, isUndef;
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unsigned SrcReg;
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MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
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if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
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SrcReg, isKill, isUndef, ImplicitOp))
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return nullptr;
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const MachineOperand &Src2 = MI->getOperand(2);
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bool isKill2, isUndef2;
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unsigned SrcReg2;
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MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
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if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
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SrcReg2, isKill2, isUndef2, ImplicitOp2))
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return nullptr;
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MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
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.addOperand(Dest);
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if (ImplicitOp.getReg() != 0)
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MIB.addOperand(ImplicitOp);
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if (ImplicitOp2.getReg() != 0)
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MIB.addOperand(ImplicitOp2);
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NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
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// Preserve undefness of the operands.
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NewMI->getOperand(1).setIsUndef(isUndef);
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NewMI->getOperand(3).setIsUndef(isUndef2);
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if (LV && Src2.isKill())
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LV->replaceKillInstruction(SrcReg2, MI, NewMI);
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break;
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}
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case X86::ADD16rr:
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case X86::ADD16rr_DB: {
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if (DisableLEA16)
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return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
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: nullptr;
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assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
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unsigned Src2 = MI->getOperand(2).getReg();
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bool isKill2 = MI->getOperand(2).isKill();
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NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
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.addOperand(Dest),
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Src.getReg(), Src.isKill(), Src2, isKill2);
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// Preserve undefness of the operands.
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bool isUndef = MI->getOperand(1).isUndef();
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bool isUndef2 = MI->getOperand(2).isUndef();
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NewMI->getOperand(1).setIsUndef(isUndef);
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NewMI->getOperand(3).setIsUndef(isUndef2);
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if (LV && isKill2)
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LV->replaceKillInstruction(Src2, MI, NewMI);
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break;
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}
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case X86::ADD64ri32:
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case X86::ADD64ri8:
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case X86::ADD64ri32_DB:
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case X86::ADD64ri8_DB:
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assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
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NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
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.addOperand(Dest).addOperand(Src),
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MI->getOperand(2).getImm());
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break;
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case X86::ADD32ri:
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case X86::ADD32ri8:
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case X86::ADD32ri_DB:
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case X86::ADD32ri8_DB: {
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assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
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unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
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bool isKill, isUndef;
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unsigned SrcReg;
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MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
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if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
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SrcReg, isKill, isUndef, ImplicitOp))
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return nullptr;
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MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
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.addOperand(Dest)
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.addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
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if (ImplicitOp.getReg() != 0)
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MIB.addOperand(ImplicitOp);
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NewMI = addOffset(MIB, MI->getOperand(2).getImm());
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break;
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}
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case X86::ADD16ri:
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case X86::ADD16ri8:
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case X86::ADD16ri_DB:
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case X86::ADD16ri8_DB:
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if (DisableLEA16)
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return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
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: nullptr;
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assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
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NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
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.addOperand(Dest).addOperand(Src),
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MI->getOperand(2).getImm());
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break;
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}
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NewMI = addOffset(MIB, 1);
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break;
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}
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case X86::INC16r:
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if (DisableLEA16)
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return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
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: nullptr;
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assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
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NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
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.addOperand(Dest).addOperand(Src), 1);
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break;
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case X86::DEC64r:
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case X86::DEC32r: {
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assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
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unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
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: (is64Bit ? X86::LEA64_32r : X86::LEA32r);
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bool isKill, isUndef;
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unsigned SrcReg;
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MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
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if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
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SrcReg, isKill, isUndef, ImplicitOp))
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return nullptr;
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MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
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.addOperand(Dest)
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.addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
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if (ImplicitOp.getReg() != 0)
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MIB.addOperand(ImplicitOp);
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NewMI = addOffset(MIB, -1);
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break;
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}
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case X86::DEC16r:
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if (DisableLEA16)
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return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
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: nullptr;
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assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
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NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
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.addOperand(Dest).addOperand(Src), -1);
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break;
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case X86::ADD64rr:
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case X86::ADD64rr_DB:
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case X86::ADD32rr:
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case X86::ADD32rr_DB: {
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assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
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unsigned Opc;
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if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
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Opc = X86::LEA64r;
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else
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Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
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bool isKill, isUndef;
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unsigned SrcReg;
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MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
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if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
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SrcReg, isKill, isUndef, ImplicitOp))
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return nullptr;
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const MachineOperand &Src2 = MI->getOperand(2);
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bool isKill2, isUndef2;
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unsigned SrcReg2;
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MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
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if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
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SrcReg2, isKill2, isUndef2, ImplicitOp2))
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return nullptr;
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MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
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.addOperand(Dest);
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if (ImplicitOp.getReg() != 0)
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MIB.addOperand(ImplicitOp);
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if (ImplicitOp2.getReg() != 0)
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MIB.addOperand(ImplicitOp2);
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NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
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// Preserve undefness of the operands.
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NewMI->getOperand(1).setIsUndef(isUndef);
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NewMI->getOperand(3).setIsUndef(isUndef2);
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if (LV && Src2.isKill())
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LV->replaceKillInstruction(SrcReg2, MI, NewMI);
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break;
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}
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case X86::ADD16rr:
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case X86::ADD16rr_DB: {
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if (DisableLEA16)
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return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
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: nullptr;
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assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
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unsigned Src2 = MI->getOperand(2).getReg();
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bool isKill2 = MI->getOperand(2).isKill();
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NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
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.addOperand(Dest),
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Src.getReg(), Src.isKill(), Src2, isKill2);
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// Preserve undefness of the operands.
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bool isUndef = MI->getOperand(1).isUndef();
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bool isUndef2 = MI->getOperand(2).isUndef();
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NewMI->getOperand(1).setIsUndef(isUndef);
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NewMI->getOperand(3).setIsUndef(isUndef2);
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if (LV && isKill2)
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LV->replaceKillInstruction(Src2, MI, NewMI);
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break;
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}
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case X86::ADD64ri32:
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case X86::ADD64ri8:
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case X86::ADD64ri32_DB:
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case X86::ADD64ri8_DB:
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assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
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NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
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.addOperand(Dest).addOperand(Src),
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MI->getOperand(2).getImm());
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break;
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case X86::ADD32ri:
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case X86::ADD32ri8:
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case X86::ADD32ri_DB:
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case X86::ADD32ri8_DB: {
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assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
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unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
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bool isKill, isUndef;
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unsigned SrcReg;
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MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
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if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
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SrcReg, isKill, isUndef, ImplicitOp))
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return nullptr;
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MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
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.addOperand(Dest)
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.addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
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if (ImplicitOp.getReg() != 0)
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MIB.addOperand(ImplicitOp);
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NewMI = addOffset(MIB, MI->getOperand(2).getImm());
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break;
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}
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case X86::ADD16ri:
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case X86::ADD16ri8:
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case X86::ADD16ri_DB:
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case X86::ADD16ri8_DB:
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if (DisableLEA16)
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return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
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: nullptr;
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assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
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NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
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.addOperand(Dest).addOperand(Src),
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MI->getOperand(2).getImm());
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break;
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}
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if (!NewMI) return nullptr;
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