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ARM: Clean up optimizeCompare in peephole, no functional change.
Use getUniqueVRegDef. Replace a loop with existing interfaces: modifiesRegister and readsRegister. Factor out code into inline functions and simplify the code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159470 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1801,6 +1801,53 @@ static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
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return false;
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}
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/// getSwappedCondition - assume the flags are set by MI(a,b), return
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/// the condition code if we modify the instructions such that flags are
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/// set by MI(b,a).
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inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) {
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switch (CC) {
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default: return ARMCC::AL;
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case ARMCC::EQ: return ARMCC::EQ;
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case ARMCC::NE: return ARMCC::NE;
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case ARMCC::HS: return ARMCC::LS;
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case ARMCC::LO: return ARMCC::HI;
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case ARMCC::HI: return ARMCC::LO;
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case ARMCC::LS: return ARMCC::HS;
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case ARMCC::GE: return ARMCC::LE;
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case ARMCC::LT: return ARMCC::GT;
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case ARMCC::GT: return ARMCC::LT;
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case ARMCC::LE: return ARMCC::GE;
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}
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}
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/// isRedundantFlagInstr - check whether the first instruction, whose only
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/// purpose is to update flags, can be made redundant.
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/// CMPrr can be made redundant by SUBrr if the operands are the same.
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/// CMPri can be made redundant by SUBri if the operands are the same.
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/// This function can be extended later on.
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inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
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unsigned SrcReg2, int ImmValue,
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MachineInstr *OI) {
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if ((CmpI->getOpcode() == ARM::CMPrr ||
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CmpI->getOpcode() == ARM::t2CMPrr) &&
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(OI->getOpcode() == ARM::SUBrr ||
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OI->getOpcode() == ARM::t2SUBrr) &&
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((OI->getOperand(1).getReg() == SrcReg &&
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OI->getOperand(2).getReg() == SrcReg2) ||
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(OI->getOperand(1).getReg() == SrcReg2 &&
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OI->getOperand(2).getReg() == SrcReg)))
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return true;
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if ((CmpI->getOpcode() == ARM::CMPri ||
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CmpI->getOpcode() == ARM::t2CMPri) &&
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(OI->getOpcode() == ARM::SUBri ||
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OI->getOpcode() == ARM::t2SUBri) &&
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OI->getOperand(1).getReg() == SrcReg &&
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OI->getOperand(2).getImm() == ImmValue)
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return true;
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return false;
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}
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/// optimizeCompareInstr - Convert the instruction supplying the argument to the
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/// comparison into one that sets the zero bit in the flags register;
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/// Remove a redundant Compare instruction if an earlier instruction can set the
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@ -1812,15 +1859,9 @@ bool ARMBaseInstrInfo::
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optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
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int CmpMask, int CmpValue,
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const MachineRegisterInfo *MRI) const {
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if (MRI->def_empty(SrcReg))
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return false;
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MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg);
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if (llvm::next(DI) != MRI->def_end())
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// Only support one definition.
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return false;
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MachineInstr *MI = &*DI;
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// Get the unique definition of SrcReg.
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MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
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if (!MI) return false;
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// Masked compares sometimes use the same register as the corresponding 'and'.
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if (CmpMask != ~0) {
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@ -1867,40 +1908,19 @@ optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
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// Check that CPSR isn't set between the comparison instruction and the one we
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// want to change. At the same time, search for Sub.
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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--I;
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for (; I != E; --I) {
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const MachineInstr &Instr = *I;
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for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) {
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const MachineOperand &MO = Instr.getOperand(IO);
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if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR))
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return false;
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if (!MO.isReg()) continue;
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if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
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Instr.readsRegister(ARM::CPSR, TRI))
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// This instruction modifies or uses CPSR after the one we want to
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// change. We can't do this transformation.
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if (MO.getReg() == ARM::CPSR)
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return false;
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}
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return false;
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// Check whether the current instruction is SUB(r1, r2) or SUB(r2, r1).
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if (SrcReg2 != 0 &&
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(Instr.getOpcode() == ARM::SUBrr ||
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Instr.getOpcode() == ARM::t2SUBrr) &&
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((Instr.getOperand(1).getReg() == SrcReg &&
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Instr.getOperand(2).getReg() == SrcReg2) ||
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(Instr.getOperand(1).getReg() == SrcReg2 &&
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Instr.getOperand(2).getReg() == SrcReg))) {
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Sub = &*I;
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break;
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}
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// Check whether the current instruction is SUBri(r1, CmpValue).
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if ((CmpInstr->getOpcode() == ARM::CMPri ||
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CmpInstr->getOpcode() == ARM::t2CMPri) &&
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Instr.getOpcode() == ARM::SUBri && CmpValue != 0 &&
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Instr.getOperand(1).getReg() == SrcReg &&
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Instr.getOperand(2).getImm() == CmpValue) {
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// Check whether CmpInstr can be made redundant by the current instruction.
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if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
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Sub = &*I;
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break;
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}
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@ -1958,7 +1978,8 @@ optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
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// CPSR use (i.e. used in another block), then it's not safe to perform
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// the optimization.
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// When checking against Sub, we handle the condition codes GE, LT, GT, LE.
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SmallVector<MachineOperand*, 4> OperandsToUpdate;
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SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4>
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OperandsToUpdate;
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bool isSafe = false;
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I = CmpInstr;
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E = CmpInstr->getParent()->end();
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@ -1979,30 +2000,20 @@ optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
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}
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// Condition code is after the operand before CPSR.
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ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm();
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if (Sub)
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switch (CC) {
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default:
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if (Sub) {
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ARMCC::CondCodes NewCC = getSwappedCondition(CC);
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if (NewCC == ARMCC::AL)
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return false;
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case ARMCC::GE:
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case ARMCC::LT:
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case ARMCC::GT:
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case ARMCC::LE:
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case ARMCC::HS:
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case ARMCC::LS:
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case ARMCC::HI:
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case ARMCC::LO:
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case ARMCC::EQ:
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case ARMCC::NE:
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// If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
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// on CMP needs to be updated to be based on SUB.
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// Push the condition code operands to OperandsToUpdate.
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// If it is safe to remove CmpInstr, the condition code of these
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// operands will be modified.
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if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
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Sub->getOperand(2).getReg() == SrcReg)
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OperandsToUpdate.push_back(&((*I).getOperand(IO-1)));
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break;
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}
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// If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
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// on CMP needs to be updated to be based on SUB.
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// Push the condition code operands to OperandsToUpdate.
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// If it is safe to remove CmpInstr, the condition code of these
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// operands will be modified.
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if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
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Sub->getOperand(2).getReg() == SrcReg)
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OperandsToUpdate.push_back(std::make_pair(&((*I).getOperand(IO-1)),
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NewCC));
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}
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else
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switch (CC) {
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default:
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@ -2032,26 +2043,8 @@ optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
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// Modify the condition code of operands in OperandsToUpdate.
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// Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
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// be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
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for (unsigned i = 0; i < OperandsToUpdate.size(); i++) {
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ARMCC::CondCodes CC = (ARMCC::CondCodes)OperandsToUpdate[i]->getImm();
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ARMCC::CondCodes NewCC;
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switch (CC) {
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default: llvm_unreachable("only expecting less/greater comparisons here");
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case ARMCC::GE: NewCC = ARMCC::LE; break;
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case ARMCC::LT: NewCC = ARMCC::GT; break;
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case ARMCC::GT: NewCC = ARMCC::LT; break;
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case ARMCC::LE: NewCC = ARMCC::GE; break;
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case ARMCC::HS: NewCC = ARMCC::LS; break;
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case ARMCC::LS: NewCC = ARMCC::HS; break;
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case ARMCC::HI: NewCC = ARMCC::LO; break;
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case ARMCC::LO: NewCC = ARMCC::HI; break;
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case ARMCC::EQ:
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case ARMCC::NE:
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NewCC = CC;
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break;
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}
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OperandsToUpdate[i]->setImm(NewCC);
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}
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for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
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OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
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return true;
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}
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}
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