mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-01 15:11:24 +00:00
For X86, change load/dec-or-inc/store into dec-or-inc, respectively.
This is a code change to add support for changing instruction sequences of the form: load inc/dec of 8/16/32/64 bits store into the appropriate X86 inc/dec through memory instruction: inc[qlwb] / dec[qlwb] The checks that were in X86DAGToDAGISel::Select(SDNode *Node)>>ISD::STORE have been extracted to isLoadIncOrDecStore and reworked to use the better named wrappers for getOperand(unsigned) (e.g. getOffset()) and replaced Chain.getNode() with LoadNode. The comments have also been expanded. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153635 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Joel Jones
parent
3c6b29b7e9
commit
76d03106df
@ -1847,6 +1847,86 @@ static bool HasNoSignedComparisonUses(SDNode *N) {
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return true;
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}
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/// isLoadIncOrDecStore - Check whether or not the chain ending in StoreNode
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/// is suitable for doing the {load; increment or decrement; store} to modify
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/// transformation.
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static bool isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc,
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SDValue &StoredVal) {
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// is the value stored the result of a DEC or INC?
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if (!(Opc == X86ISD::DEC || Opc == X86ISD::INC)) return false;
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// is the chain predecessor to the store a load?
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SDValue Chain = StoreNode->getChain();
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if (Chain->getOpcode() != ISD::LOAD) return false;
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// is the size of the value one that we can handle? (i.e. 64, 32, 16, or 8)
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LoadSDNode *LoadNode = cast<LoadSDNode>(Chain.getNode());
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EVT LdVT = LoadNode->getMemoryVT();
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if (LdVT != MVT::i64 && LdVT != MVT::i32 && LdVT != MVT::i16 &&
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LdVT != MVT::i8)
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return false;
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// quick check of whether the store is simple
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SDValue Undef = StoreNode->getOffset();
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if (Undef->getOpcode() != ISD::UNDEF) return false;
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// is the stored value result 0 of the load?
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if (StoredVal.getResNo() != 0) return false;
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// are there other uses of the loaded value than the inc or dec?
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if (!StoredVal.getNode()->hasNUsesOfValue(1, 0)) return false;
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// is there exactly one use of the load?
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if (!LoadNode->hasNUsesOfValue(1, 0)) return false;
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// are the load and store connected by the chain?
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if (StoredVal->getOperand(0).getNode() != LoadNode) return false;
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//OPC_CheckPredicate, 1, // Predicate_nontemporalstore
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if (StoreNode->isNonTemporal())
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return false;
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// is the address of the store the same as the load?
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SDValue Address = StoreNode->getBasePtr();
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if (LoadNode->getBasePtr() != Address ||
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LoadNode->getOffset() != Undef)
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return false;
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// is the load non-extending and non-indexed?
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if (!ISD::isNormalLoad(LoadNode))
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return false;
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// is the store non-extending and non-indexed?
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if (!ISD::isNormalStore(StoreNode))
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return false;
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// check load chain has only one use (from the store)
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if (!Chain.hasOneUse())
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return false;
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return true;
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}
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/// getFusedLdStOpcode - Get the appropriate X86 opcode for an in memory
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/// increment or decrement. Opc should be X86ISD::DEC or X86ISD:INC.
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static unsigned getFusedLdStOpcode(EVT &LdVT, unsigned Opc) {
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if (Opc == X86ISD::DEC) {
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if (LdVT == MVT::i64) return X86::DEC64m;
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if (LdVT == MVT::i32) return X86::DEC32m;
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if (LdVT == MVT::i16) return X86::DEC16m;
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if (LdVT == MVT::i8) return X86::DEC8m;
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assert(0 && "unrecognized size for LdVT");
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}
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else {
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if (LdVT == MVT::i64) return X86::INC64m;
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if (LdVT == MVT::i32) return X86::INC32m;
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if (LdVT == MVT::i16) return X86::INC16m;
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if (LdVT == MVT::i8) return X86::INC8m;
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assert(0 && "unrecognized size for LdVT");
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}
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}
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SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
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EVT NVT = Node->getValueType(0);
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unsigned Opc, MOpc;
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@ -2354,9 +2434,13 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
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break;
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}
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case ISD::STORE: {
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// Change a chain of {load; incr or dec; store} of the same value into
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// a simple increment or decrement through memory of that value, if the
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// uses of the modified value and its address are suitable.
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// The DEC64m tablegen pattern is currently not able to match the case where
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// the EFLAGS on the original DEC are used.
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// we'll need to improve tablegen to allow flags to be transferred from a
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// the EFLAGS on the original DEC are used. (This also applies to
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// {INC,DEC}X{64,32,16,8}.)
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// We'll need to improve tablegen to allow flags to be transferred from a
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// node in the pattern to the result node. probably with a new keyword
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// for example, we have this
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// def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
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@ -2366,42 +2450,16 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
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// def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
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// [(store (add (loadi64 addr:$dst), -1), addr:$dst),
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// (transferrable EFLAGS)]>;
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StoreSDNode *StoreNode = cast<StoreSDNode>(Node);
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SDValue Chain = StoreNode->getOperand(0);
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SDValue StoredVal = StoreNode->getOperand(1);
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SDValue Address = StoreNode->getOperand(2);
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SDValue Undef = StoreNode->getOperand(3);
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unsigned Opc = StoredVal->getOpcode();
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if (StoreNode->getMemOperand()->getSize() != 8 ||
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Undef->getOpcode() != ISD::UNDEF ||
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Chain->getOpcode() != ISD::LOAD ||
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StoredVal->getOpcode() != X86ISD::DEC ||
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StoredVal.getResNo() != 0 ||
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!StoredVal.getNode()->hasNUsesOfValue(1, 0) ||
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!Chain.getNode()->hasNUsesOfValue(1, 0) ||
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StoredVal->getOperand(0).getNode() != Chain.getNode())
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break;
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//OPC_CheckPredicate, 1, // Predicate_nontemporalstore
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if (StoreNode->isNonTemporal())
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break;
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LoadSDNode *LoadNode = cast<LoadSDNode>(Chain.getNode());
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if (LoadNode->getOperand(1) != Address ||
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LoadNode->getOperand(2) != Undef)
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break;
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if (!ISD::isNormalLoad(LoadNode))
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break;
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if (!ISD::isNormalStore(StoreNode))
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break;
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// check load chain has only one use (from the store)
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if (!Chain.hasOneUse())
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break;
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if (!isLoadIncOrDecStore(StoreNode, Opc, StoredVal)) break;
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// Merge the input chains if they are not intra-pattern references.
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SDValue Chain = StoreNode->getOperand(0);
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LoadSDNode *LoadNode = cast<LoadSDNode>(Chain.getNode());
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SDValue InputChain = LoadNode->getOperand(0);
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SDValue Base, Scale, Index, Disp, Segment;
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@ -2413,7 +2471,9 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
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MemOp[0] = StoreNode->getMemOperand();
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MemOp[1] = LoadNode->getMemOperand();
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const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain };
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MachineSDNode *Result = CurDAG->getMachineNode(X86::DEC64m,
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EVT LdVT = LoadNode->getMemoryVT();
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unsigned newOpc = getFusedLdStOpcode(LdVT, Opc);
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MachineSDNode *Result = CurDAG->getMachineNode(newOpc,
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Node->getDebugLoc(),
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MVT::i32, MVT::Other, Ops,
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array_lengthof(Ops));
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@ -1,67 +0,0 @@
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; RUN: llc < %s -march=x86-64 | FileCheck %s
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%struct.obj = type { i64 }
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; CHECK: _Z7releaseP3obj
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define void @_Z7releaseP3obj(%struct.obj* nocapture %o) nounwind uwtable ssp {
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entry:
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; CHECK: decq (%{{rdi|rcx}})
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; CHECK-NEXT: je
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%refcnt = getelementptr inbounds %struct.obj* %o, i64 0, i32 0
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%0 = load i64* %refcnt, align 8, !tbaa !0
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%dec = add i64 %0, -1
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store i64 %dec, i64* %refcnt, align 8, !tbaa !0
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%tobool = icmp eq i64 %dec, 0
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br i1 %tobool, label %if.end, label %return
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if.end: ; preds = %entry
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%1 = bitcast %struct.obj* %o to i8*
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tail call void @free(i8* %1)
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br label %return
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return: ; preds = %entry, %if.end
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ret void
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}
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@c = common global i64 0, align 8
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@a = common global i32 0, align 4
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@.str = private unnamed_addr constant [5 x i8] c"%ld\0A\00", align 1
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@b = common global i32 0, align 4
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; CHECK: test
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define i32 @test() nounwind uwtable ssp {
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entry:
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; CHECK: decq
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; CHECK-NOT: decq
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%0 = load i64* @c, align 8, !tbaa !0
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%dec.i = add nsw i64 %0, -1
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store i64 %dec.i, i64* @c, align 8, !tbaa !0
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%tobool.i = icmp ne i64 %dec.i, 0
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%lor.ext.i = zext i1 %tobool.i to i32
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store i32 %lor.ext.i, i32* @a, align 4, !tbaa !3
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%call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i64 0, i64 0), i64 %dec.i) nounwind
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ret i32 0
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}
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; CHECK: test2
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define i32 @test2() nounwind uwtable ssp {
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entry:
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; CHECK-NOT: decq ({{.*}})
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%0 = load i64* @c, align 8, !tbaa !0
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%dec.i = add nsw i64 %0, -1
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store i64 %dec.i, i64* @c, align 8, !tbaa !0
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%tobool.i = icmp ne i64 %0, 0
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%lor.ext.i = zext i1 %tobool.i to i32
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store i32 %lor.ext.i, i32* @a, align 4, !tbaa !3
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%call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i64 0, i64 0), i64 %dec.i) nounwind
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ret i32 0
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}
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declare i32 @printf(i8* nocapture, ...) nounwind
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declare void @free(i8* nocapture) nounwind
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!0 = metadata !{metadata !"long", metadata !1}
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!1 = metadata !{metadata !"omnipotent char", metadata !2}
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!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
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!3 = metadata !{metadata !"int", metadata !1}
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179
test/CodeGen/X86/rd-mod-wr-eflags.ll
Normal file
179
test/CodeGen/X86/rd-mod-wr-eflags.ll
Normal file
@ -0,0 +1,179 @@
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; RUN: llc < %s -march=x86-64 | FileCheck %s
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%struct.obj = type { i64 }
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; CHECK: _Z7releaseP3obj
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define void @_Z7releaseP3obj(%struct.obj* nocapture %o) nounwind uwtable ssp {
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entry:
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; CHECK: decq (%{{rdi|rcx}})
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; CHECK-NEXT: je
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%refcnt = getelementptr inbounds %struct.obj* %o, i64 0, i32 0
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%0 = load i64* %refcnt, align 8, !tbaa !0
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%dec = add i64 %0, -1
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store i64 %dec, i64* %refcnt, align 8, !tbaa !0
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%tobool = icmp eq i64 %dec, 0
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br i1 %tobool, label %if.end, label %return
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if.end: ; preds = %entry
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%1 = bitcast %struct.obj* %o to i8*
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tail call void @free(i8* %1)
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br label %return
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return: ; preds = %entry, %if.end
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ret void
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}
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@c = common global i64 0, align 8
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@a = common global i32 0, align 4
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@.str = private unnamed_addr constant [5 x i8] c"%ld\0A\00", align 1
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@b = common global i32 0, align 4
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; CHECK: test
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define i32 @test() nounwind uwtable ssp {
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entry:
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; CHECK: decq
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; CHECK-NOT: decq
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%0 = load i64* @c, align 8, !tbaa !0
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%dec.i = add nsw i64 %0, -1
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store i64 %dec.i, i64* @c, align 8, !tbaa !0
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%tobool.i = icmp ne i64 %dec.i, 0
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%lor.ext.i = zext i1 %tobool.i to i32
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store i32 %lor.ext.i, i32* @a, align 4, !tbaa !3
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%call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i64 0, i64 0), i64 %dec.i) nounwind
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ret i32 0
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}
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; CHECK: test2
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define i32 @test2() nounwind uwtable ssp {
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entry:
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; CHECK-NOT: decq ({{.*}})
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%0 = load i64* @c, align 8, !tbaa !0
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%dec.i = add nsw i64 %0, -1
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store i64 %dec.i, i64* @c, align 8, !tbaa !0
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%tobool.i = icmp ne i64 %0, 0
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%lor.ext.i = zext i1 %tobool.i to i32
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store i32 %lor.ext.i, i32* @a, align 4, !tbaa !3
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%call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i64 0, i64 0), i64 %dec.i) nounwind
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ret i32 0
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}
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declare i32 @printf(i8* nocapture, ...) nounwind
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declare void @free(i8* nocapture) nounwind
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!0 = metadata !{metadata !"long", metadata !1}
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!1 = metadata !{metadata !"omnipotent char", metadata !2}
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!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
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!3 = metadata !{metadata !"int", metadata !1}
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%struct.obj2 = type { i64, i32, i16, i8 }
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declare void @other(%struct.obj2* ) nounwind;
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; CHECK: example_dec
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define void @example_dec(%struct.obj2* %o) nounwind uwtable ssp {
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; 64 bit dec
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entry:
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%s64 = getelementptr inbounds %struct.obj2* %o, i64 0, i32 0
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; CHECK-NOT: load
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%0 = load i64* %s64, align 8
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; CHECK: decq ({{.*}})
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%dec = add i64 %0, -1
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store i64 %dec, i64* %s64, align 8
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%tobool = icmp eq i64 %dec, 0
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br i1 %tobool, label %if.end, label %return
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; 32 bit dec
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if.end:
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%s32 = getelementptr inbounds %struct.obj2* %o, i64 0, i32 1
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; CHECK-NOT: load
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%1 = load i32* %s32, align 4
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; CHECK: decl {{[0-9][0-9]*}}({{.*}})
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%dec1 = add i32 %1, -1
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store i32 %dec1, i32* %s32, align 4
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%tobool2 = icmp eq i32 %dec1, 0
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br i1 %tobool2, label %if.end1, label %return
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; 16 bit dec
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if.end1:
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%s16 = getelementptr inbounds %struct.obj2* %o, i64 0, i32 2
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; CHECK-NOT: load
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%2 = load i16* %s16, align 2
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; CHECK: decw {{[0-9][0-9]*}}({{.*}})
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%dec2 = add i16 %2, -1
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store i16 %dec2, i16* %s16, align 2
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%tobool3 = icmp eq i16 %dec2, 0
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br i1 %tobool3, label %if.end2, label %return
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; 8 bit dec
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if.end2:
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%s8 = getelementptr inbounds %struct.obj2* %o, i64 0, i32 3
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; CHECK-NOT: load
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%3 = load i8* %s8
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; CHECK: decb {{[0-9][0-9]*}}({{.*}})
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%dec3 = add i8 %3, -1
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store i8 %dec3, i8* %s8
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%tobool4 = icmp eq i8 %dec3, 0
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br i1 %tobool4, label %if.end4, label %return
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if.end4:
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tail call void @other(%struct.obj2* %o) nounwind
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br label %return
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return: ; preds = %if.end4, %if.end, %entry
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ret void
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}
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; CHECK: example_inc
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define void @example_inc(%struct.obj2* %o) nounwind uwtable ssp {
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; 64 bit inc
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entry:
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%s64 = getelementptr inbounds %struct.obj2* %o, i64 0, i32 0
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; CHECK-NOT: load
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%0 = load i64* %s64, align 8
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; CHECK: incq ({{.*}})
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%inc = add i64 %0, 1
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store i64 %inc, i64* %s64, align 8
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%tobool = icmp eq i64 %inc, 0
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br i1 %tobool, label %if.end, label %return
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; 32 bit inc
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if.end:
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%s32 = getelementptr inbounds %struct.obj2* %o, i64 0, i32 1
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; CHECK-NOT: load
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%1 = load i32* %s32, align 4
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; CHECK: incl {{[0-9][0-9]*}}({{.*}})
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%inc1 = add i32 %1, 1
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store i32 %inc1, i32* %s32, align 4
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%tobool2 = icmp eq i32 %inc1, 0
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br i1 %tobool2, label %if.end1, label %return
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; 16 bit inc
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if.end1:
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%s16 = getelementptr inbounds %struct.obj2* %o, i64 0, i32 2
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; CHECK-NOT: load
|
||||
%2 = load i16* %s16, align 2
|
||||
; CHECK: incw {{[0-9][0-9]*}}({{.*}})
|
||||
%inc2 = add i16 %2, 1
|
||||
store i16 %inc2, i16* %s16, align 2
|
||||
%tobool3 = icmp eq i16 %inc2, 0
|
||||
br i1 %tobool3, label %if.end2, label %return
|
||||
|
||||
; 8 bit inc
|
||||
if.end2:
|
||||
%s8 = getelementptr inbounds %struct.obj2* %o, i64 0, i32 3
|
||||
; CHECK-NOT: load
|
||||
%3 = load i8* %s8
|
||||
; CHECK: incb {{[0-9][0-9]*}}({{.*}})
|
||||
%inc3 = add i8 %3, 1
|
||||
store i8 %inc3, i8* %s8
|
||||
%tobool4 = icmp eq i8 %inc3, 0
|
||||
br i1 %tobool4, label %if.end4, label %return
|
||||
|
||||
if.end4:
|
||||
tail call void @other(%struct.obj2* %o) nounwind
|
||||
br label %return
|
||||
|
||||
return:
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user