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Reapply 91904.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91996 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -36,7 +36,10 @@ class VISIBILITY_HIDDEN PIC16DAGToDAGISel : public SelectionDAGISel {
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public:
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explicit PIC16DAGToDAGISel(PIC16TargetMachine &tm) :
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SelectionDAGISel(tm),
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TM(tm), PIC16Lowering(*TM.getTargetLowering()) {}
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TM(tm), PIC16Lowering(*TM.getTargetLowering()) {
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// Keep PIC16 specific DAGISel to use during the lowering
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PIC16Lowering.ISel = this;
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}
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// Pass Name
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virtual const char *getPassName() const {
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@ -1482,7 +1482,8 @@ bool PIC16TargetLowering::isDirectLoad(const SDValue Op) {
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// operand no. of the operand to be converted in 'MemOp'. Remember, PIC16 has
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// no instruction that can operation on two registers. Most insns take
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// one register and one memory operand (addwf) / Constant (addlw).
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bool PIC16TargetLowering::NeedToConvertToMemOp(SDValue Op, unsigned &MemOp) {
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bool PIC16TargetLowering::NeedToConvertToMemOp(SDValue Op, unsigned &MemOp,
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SelectionDAG &DAG) {
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// If one of the operand is a constant, return false.
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if (Op.getOperand(0).getOpcode() == ISD::Constant ||
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Op.getOperand(1).getOpcode() == ISD::Constant)
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@ -1491,11 +1492,33 @@ bool PIC16TargetLowering::NeedToConvertToMemOp(SDValue Op, unsigned &MemOp) {
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// Return false if one of the operands is already a direct
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// load and that operand has only one use.
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if (isDirectLoad(Op.getOperand(0))) {
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if (Op.getOperand(0).hasOneUse())
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if (Op.getOperand(0).hasOneUse()) {
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// Legal and profitable folding check uses the NodeId of DAG nodes.
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// This NodeId is assigned by topological order. Therefore first
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// assign topological order then perform legal and profitable check.
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// Note:- Though this ordering is done before begining with legalization,
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// newly added node during legalization process have NodeId=-1 (NewNode)
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// therefore before performing any check proper ordering of the node is
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// required.
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DAG.AssignTopologicalOrder();
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// Direct load operands are folded in binary operations. But before folding
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// verify if this folding is legal. Fold only if it is legal otherwise
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// convert this direct load to a separate memory operation.
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if(ISel->IsLegalAndProfitableToFold(Op.getOperand(0).getNode(),
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Op.getNode(), Op.getNode()))
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return false;
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else
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MemOp = 0;
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}
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}
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// For operations that are non-cummutative there is no need to check
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// for right operand because folding right operand may result in
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// incorrect operation.
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if (! SelectionDAG::isCommutativeBinOp(Op.getOpcode()))
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return true;
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if (isDirectLoad(Op.getOperand(1))) {
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if (Op.getOperand(1).hasOneUse())
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return false;
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@ -1514,7 +1537,7 @@ SDValue PIC16TargetLowering::LowerBinOp(SDValue Op, SelectionDAG &DAG) {
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assert (Op.getValueType() == MVT::i8 && "illegal Op to lower");
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unsigned MemOp = 1;
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if (NeedToConvertToMemOp(Op, MemOp)) {
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if (NeedToConvertToMemOp(Op, MemOp, DAG)) {
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// Put one value on stack.
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SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
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@ -1533,7 +1556,7 @@ SDValue PIC16TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) {
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assert (Op.getValueType() == MVT::i8 && "illegal add to lower");
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DebugLoc dl = Op.getDebugLoc();
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unsigned MemOp = 1;
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if (NeedToConvertToMemOp(Op, MemOp)) {
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if (NeedToConvertToMemOp(Op, MemOp, DAG)) {
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// Put one value on stack.
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SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
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@ -1574,7 +1597,7 @@ SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) {
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DAG.getConstant(0-(C->getZExtValue()), MVT::i8));
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}
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if (NeedToConvertToMemOp(Op, MemOp) ||
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if (NeedToConvertToMemOp(Op, MemOp, DAG) ||
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(isDirectLoad(Op.getOperand(1)) &&
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(!isDirectLoad(Op.getOperand(0))) &&
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(Op.getOperand(0).getOpcode() != ISD::Constant)))
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@ -18,6 +18,7 @@
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#include "PIC16.h"
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#include "PIC16Subtarget.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetLowering.h"
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#include <map>
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@ -216,7 +217,9 @@ namespace llvm {
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// This function checks if we need to put an operand of an operation on
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// stack and generate a load or not.
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bool NeedToConvertToMemOp(SDValue Op, unsigned &MemOp);
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// DAG parameter is required to access DAG information during
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// analysis.
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bool NeedToConvertToMemOp(SDValue Op, unsigned &MemOp, SelectionDAG &DAG);
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/// Subtarget - Keep a pointer to the PIC16Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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@ -239,6 +242,11 @@ namespace llvm {
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// Check if operation has a direct load operand.
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inline bool isDirectLoad(const SDValue Op);
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public:
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// Keep a pointer to SelectionDAGISel to access its public
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// interface (It is required during legalization)
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SelectionDAGISel *ISel;
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private:
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// The frameindexes generated for spill/reload are stack based.
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// This maps maintain zero based indexes for these FIs.
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15
test/CodeGen/PIC16/C16-49.ll
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15
test/CodeGen/PIC16/C16-49.ll
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@ -0,0 +1,15 @@
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;RUN: llvm-as < %s | llc -march=pic16
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@aa = global i16 55, align 1 ; <i16*> [#uses=1]
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@bb = global i16 44, align 1 ; <i16*> [#uses=1]
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@PORTD = external global i8 ; <i8*> [#uses=1]
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define void @foo() nounwind {
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entry:
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%tmp = volatile load i16* @aa ; <i16> [#uses=1]
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%tmp1 = volatile load i16* @bb ; <i16> [#uses=1]
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%sub = sub i16 %tmp, %tmp1 ; <i16> [#uses=1]
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%conv = trunc i16 %sub to i8 ; <i8> [#uses=1]
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store i8 %conv, i8* @PORTD
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ret void
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}
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