mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-08-05 13:26:55 +00:00
Adding SSSE3 intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
@@ -128,6 +128,11 @@ def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
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def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
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def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
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def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
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def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop node:$ptr))>;
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def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
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def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop node:$ptr))>;
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def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop node:$ptr))>;
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def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop node:$ptr))>;
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def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
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def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
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@@ -2281,35 +2286,297 @@ let AddedComplexity = 20 in
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// SSE3 Instruction Templates:
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//
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// SS38I - SSSE3 instructions with T8 and OpSize prefixes.
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// SS3AI - SSSE3 instructions with TA and OpSize prefixes.
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// SS38I - SSSE3 instructions with T8 prefix.
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// SS3AI - SSSE3 instructions with TA prefix.
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class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, T8, OpSize, Requires<[HasSSSE3]>;
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: I<o, F, outs, ins, asm, pattern>, T8, Requires<[HasSSSE3]>;
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class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TA, OpSize, Requires<[HasSSSE3]>;
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: I<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSSE3]>;
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/// SS3I_binop_rm_int - Simple SSSE3 binary operatr whose type is v2i64.
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/// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
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let isTwoAddress = 1 in {
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multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
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bit Commutable = 0> {
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def rr : SS38I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
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multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
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Intrinsic IntId64, Intrinsic IntId128,
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bit Commutable = 0> {
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def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR64:$dst, (IntId64 VR64:$src))]> {
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let isCommutable = Commutable;
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}
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def rm : SS38I<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst,
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(IntId VR128:$src1,
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(bitconvert (memopv2i64 addr:$src2))))]>;
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def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR64:$dst,
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(IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
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def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (IntId128 VR128:$src))]>,
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OpSize {
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let isCommutable = Commutable;
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}
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def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins i128mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst,
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(IntId128
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(bitconvert (memopv16i8 addr:$src))))]>, OpSize;
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}
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}
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defm PMULHRSW128 : SS3I_binop_rm_int<0x0B, "pmulhrsw",
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int_x86_ssse3_pmulhrsw_128, 1>;
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/// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
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let isTwoAddress = 1 in {
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multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
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Intrinsic IntId64, Intrinsic IntId128,
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bit Commutable = 0> {
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def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR64:$dst, (IntId64 VR64:$src))]> {
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let isCommutable = Commutable;
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}
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def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
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(ins i64mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR64:$dst,
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(IntId64
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(bitconvert (memopv4i16 addr:$src))))]>;
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def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (IntId128 VR128:$src))]>,
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OpSize {
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let isCommutable = Commutable;
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}
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def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins i128mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst,
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(IntId128
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(bitconvert (memopv8i16 addr:$src))))]>, OpSize;
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}
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}
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/// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
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let isTwoAddress = 1 in {
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multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
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Intrinsic IntId64, Intrinsic IntId128,
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bit Commutable = 0> {
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def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR64:$dst, (IntId64 VR64:$src))]> {
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let isCommutable = Commutable;
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}
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def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
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(ins i64mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR64:$dst,
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(IntId64
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(bitconvert (memopv2i32 addr:$src))))]>;
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def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (IntId128 VR128:$src))]>,
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OpSize {
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let isCommutable = Commutable;
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}
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def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins i128mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst,
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(IntId128
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(bitconvert (memopv4i32 addr:$src))))]>, OpSize;
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}
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}
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defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
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int_x86_ssse3_pabs_b,
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int_x86_ssse3_pabs_b_128>;
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defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
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int_x86_ssse3_pabs_w,
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int_x86_ssse3_pabs_w_128>;
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defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
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int_x86_ssse3_pabs_d,
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int_x86_ssse3_pabs_d_128>;
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/// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
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let isTwoAddress = 1 in {
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multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
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Intrinsic IntId64, Intrinsic IntId128,
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bit Commutable = 0> {
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def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
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let isCommutable = Commutable;
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}
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def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst,
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(IntId64 VR64:$src1,
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(bitconvert (memopv8i8 addr:$src2))))]>;
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def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
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OpSize {
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let isCommutable = Commutable;
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}
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def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst,
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(IntId128 VR128:$src1,
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(bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
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}
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}
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/// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
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let isTwoAddress = 1 in {
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multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
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Intrinsic IntId64, Intrinsic IntId128,
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bit Commutable = 0> {
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def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
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let isCommutable = Commutable;
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}
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def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst,
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(IntId64 VR64:$src1,
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(bitconvert (memopv4i16 addr:$src2))))]>;
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def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
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OpSize {
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let isCommutable = Commutable;
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}
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def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst,
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(IntId128 VR128:$src1,
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(bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
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}
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}
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/// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
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let isTwoAddress = 1 in {
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multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
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Intrinsic IntId64, Intrinsic IntId128,
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bit Commutable = 0> {
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def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
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let isCommutable = Commutable;
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}
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def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst,
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(IntId64 VR64:$src1,
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(bitconvert (memopv2i32 addr:$src2))))]>;
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def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
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OpSize {
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let isCommutable = Commutable;
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}
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def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst,
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(IntId128 VR128:$src1,
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(bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
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}
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}
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defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
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int_x86_ssse3_phadd_w,
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int_x86_ssse3_phadd_w_128, 1>;
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defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
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int_x86_ssse3_phadd_d,
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int_x86_ssse3_phadd_d_128, 1>;
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defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
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int_x86_ssse3_phadd_sw,
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int_x86_ssse3_phadd_sw_128, 1>;
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defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
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int_x86_ssse3_phsub_w,
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int_x86_ssse3_phsub_w_128>;
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defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
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int_x86_ssse3_phsub_d,
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int_x86_ssse3_phsub_d_128>;
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defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
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int_x86_ssse3_phsub_sw,
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int_x86_ssse3_phsub_sw_128>;
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defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
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int_x86_ssse3_pmadd_ub_sw,
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int_x86_ssse3_pmadd_ub_sw_128, 1>;
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defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
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int_x86_ssse3_pmul_hr_sw,
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int_x86_ssse3_pmul_hr_sw_128, 1>;
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defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
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int_x86_ssse3_pshuf_b,
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int_x86_ssse3_pshuf_b_128>;
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defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
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int_x86_ssse3_psign_b,
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int_x86_ssse3_psign_b_128>;
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defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
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int_x86_ssse3_psign_w,
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int_x86_ssse3_psign_w_128>;
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defm PSIGND : SS3I_binop_rm_int_32<0x09, "psignd",
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int_x86_ssse3_psign_d,
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int_x86_ssse3_psign_d_128>;
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let isTwoAddress = 1 in {
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def PALIGN64rr : SS38I<0x0F, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2, i16imm:$src3),
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"palignr\t{$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(int_x86_ssse3_palign_r
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VR64:$src1, VR64:$src2,
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imm:$src3))]>;
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def PALIGN64rm : SS38I<0x0F, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2, i16imm:$src3),
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"palignr\t{$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(int_x86_ssse3_palign_r
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VR64:$src1,
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(bitconvert (memopv2i32 addr:$src2)),
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imm:$src3))]>;
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def PALIGN128rr : SS38I<0x0F, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, i32imm:$src3),
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"palignr\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(int_x86_ssse3_palign_r_128
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VR128:$src1, VR128:$src2,
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imm:$src3))]>, OpSize;
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def PALIGN128rm : SS38I<0x0F, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, i32imm:$src3),
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"palignr\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(int_x86_ssse3_palign_r_128
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VR128:$src1,
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(bitconvert (memopv4i32 addr:$src2)),
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imm:$src3))]>, OpSize;
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}
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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Block a user