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For fastcc on x86, let ECX be used as a return register after EAX and EDX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91410 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -64,11 +64,18 @@ def RetCC_X86_32_C : CallingConv<[
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// X86-32 FastCC return-value convention.
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def RetCC_X86_32_Fast : CallingConv<[
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// The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
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// SSE2, otherwise it is the the C calling conventions.
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// SSE2.
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// This can happen when a float, 2 x float, or 3 x float vector is split by
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// target lowering, and is returned in 1-3 sse regs.
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CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
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CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
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// For integers, ECX can be used as an extra return register
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CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>,
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CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
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CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
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// Otherwise, it is the same as the common X86 calling convention.
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CCDelegateTo<RetCC_X86Common>
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]>;
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15
test/CodeGen/X86/fastcc3struct.ll
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15
test/CodeGen/X86/fastcc3struct.ll
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@ -0,0 +1,15 @@
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; RUN: llc < %s -march=x86 -o %t
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; RUN: grep "movl .48, %ecx" %t
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; RUN: grep "movl .24, %edx" %t
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; RUN: grep "movl .12, %eax" %t
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%0 = type { i32, i32, i32 }
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define internal fastcc %0 @ReturnBigStruct() nounwind readnone {
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entry:
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%0 = insertvalue %0 zeroinitializer, i32 12, 0
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%1 = insertvalue %0 %0, i32 24, 1
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%2 = insertvalue %0 %1, i32 48, 2
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ret %0 %2
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}
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