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Refactor T1sI and T1sIt encodings into helper classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120518 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
parent
52ed867801
commit
76f4e10388
@ -708,7 +708,38 @@ def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
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// Arithmetic Instructions.
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//
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// Helper classes to encode the various T1sIt patterns.
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// Helper classes for encoding T1sI patterns:
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class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: T1sI<oops, iops, itin, opc, asm, pattern>,
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T1DataProcessing<opA> {
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bits<3> Rd;
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bits<3> Rn;
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let Inst{5-3} = Rn;
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let Inst{2-0} = Rd;
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}
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class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: T1sI<oops, iops, itin, opc, asm, pattern>,
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T1General<opA> {
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bits<3> Rm;
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bits<3> Rn;
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bits<3> Rd;
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let Inst{8-6} = Rm;
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let Inst{5-3} = Rn;
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let Inst{2-0} = Rd;
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}
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class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: T1sI<oops, iops, itin, opc, asm, pattern>,
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T1General<opA> {
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bits<3> Rd;
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bits<3> Rm;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rd;
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}
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// Helper classes for encoding T1sIt patterns:
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class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: T1sIt<oops, iops, itin, opc, asm, pattern>,
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@ -736,17 +767,12 @@ def tADC : // A8.6.2
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[(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
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// Add immediate
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def tADDi3 : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, i32imm:$imm3), IIC_iALUi,
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"add", "\t$Rd, $Rn, $imm3",
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[(set tGPR:$Rd, (add tGPR:$Rn, imm0_7:$imm3))]>,
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T1General<0b01110> {
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// A8.6.4 T1
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bits<3> Rd;
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bits<3> Rn;
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def tADDi3 : // A8.6.4 T1
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T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3), IIC_iALUi,
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"add", "\t$Rd, $Rm, $imm3",
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[(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
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bits<3> imm3;
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let Inst{8-6} = imm3;
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let Inst{5-3} = Rn;
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let Inst{2-0} = Rd;
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}
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def tADDi8 : // A8.6.4 T2
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@ -757,18 +783,11 @@ def tADDi8 : // A8.6.4 T2
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// Add register
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let isCommutable = 1 in
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def tADDrr : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
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"add", "\t$Rd, $Rn, $Rm",
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[(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>,
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T1General<0b01100> {
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// A8.6.6 T1
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bits<3> Rm;
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bits<3> Rn;
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bits<3> Rd;
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let Inst{8-6} = Rm;
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let Inst{5-3} = Rn;
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let Inst{2-0} = Rd;
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}
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def tADDrr : // A8.6.6 T1
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T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iALUr,
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"add", "\t$Rd, $Rn, $Rm",
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[(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
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let neverHasSideEffects = 1 in
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def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
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@ -791,17 +810,13 @@ def tAND : // A8.6.12
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[(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
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// ASR immediate
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def tASRri : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), IIC_iMOVsi,
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"asr", "\t$Rd, $Rm, $imm5",
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[(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm:$imm5)))]>,
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T1General<{0,1,0,?,?}> {
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// A8.6.14
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bits<3> Rd;
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bits<3> Rm;
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def tASRri : // A8.6.14
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T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
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IIC_iMOVsi,
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"asr", "\t$Rd, $Rm, $imm5",
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[(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm:$imm5)))]> {
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bits<5> imm5;
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let Inst{10-6} = imm5;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rd;
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}
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// ASR register
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@ -916,17 +931,13 @@ def tEOR : // A8.6.45
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[(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
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// LSL immediate
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def tLSLri : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), IIC_iMOVsi,
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"lsl", "\t$Rd, $Rm, $imm5",
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[(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>,
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T1General<{0,0,0,?,?}> {
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// A8.6.88
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bits<3> Rd;
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bits<3> Rm;
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def tLSLri : // A8.6.88
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T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
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IIC_iMOVsi,
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"lsl", "\t$Rd, $Rm, $imm5",
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[(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
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bits<5> imm5;
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let Inst{10-6} = imm5;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rd;
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}
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// LSL register
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@ -937,17 +948,13 @@ def tLSLrr : // A8.6.89
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[(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
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// LSR immediate
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def tLSRri : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), IIC_iMOVsi,
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"lsr", "\t$Rd, $Rm, $imm5",
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[(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm:$imm5)))]>,
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T1General<{0,0,1,?,?}> {
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// A8.6.90
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bits<3> Rd;
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bits<3> Rm;
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def tLSRri : // A8.6.90
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T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
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IIC_iMOVsi,
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"lsr", "\t$Rd, $Rm, $imm5",
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[(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm:$imm5)))]> {
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bits<5> imm5;
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let Inst{10-6} = imm5;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rd;
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}
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// LSR register
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@ -1003,17 +1010,11 @@ def tMUL : // A8.6.105 T1
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"mul", "\t$Rdn, $Rm, $Rdn",
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[(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
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// move inverse register
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def tMVN : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMVNr,
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"mvn", "\t$Rd, $Rm",
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[(set tGPR:$Rd, (not tGPR:$Rm))]>,
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T1DataProcessing<0b1111> {
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// A8.6.107
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bits<3> Rd;
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bits<3> Rm;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rd;
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}
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// Move inverse register
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def tMVN : // A8.6.107
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T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
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"mvn", "\t$Rd, $Rn",
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[(set tGPR:$Rd, (not tGPR:$Rn))]>;
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// Bitwise or register
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let isCommutable = 1 in
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@ -1075,16 +1076,11 @@ def tROR : // A8.6.139
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[(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
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// Negate register
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def tRSB : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iALUi,
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"rsb", "\t$Rd, $Rn, #0",
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[(set tGPR:$Rd, (ineg tGPR:$Rn))]>,
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T1DataProcessing<0b1001> {
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// A8.6.141
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bits<3> Rn;
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bits<3> Rd;
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let Inst{5-3} = Rn;
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let Inst{2-0} = Rd;
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}
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def tRSB : // A8.6.141
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T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
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IIC_iALUi,
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"rsb", "\t$Rd, $Rn, #0",
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[(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
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// Subtract with carry register
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let Uses = [CPSR] in
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@ -1095,17 +1091,13 @@ def tSBC : // A8.6.151
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[(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
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// Subtract immediate
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def tSUBi3 : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, i32imm:$imm3), IIC_iALUi,
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"sub", "\t$Rd, $Rn, $imm3",
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[(set tGPR:$Rd, (add tGPR:$Rn, imm0_7_neg:$imm3))]>,
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T1General<0b01111> {
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// A8.6.210 T1
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def tSUBi3 : // A8.6.210 T1
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T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
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IIC_iALUi,
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"sub", "\t$Rd, $Rm, $imm3",
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[(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
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bits<3> imm3;
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bits<3> Rn;
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bits<3> Rd;
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let Inst{8-6} = imm3;
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let Inst{5-3} = Rn;
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let Inst{2-0} = Rd;
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}
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def tSUBi8 : // A8.6.210 T2
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@ -1114,23 +1106,16 @@ def tSUBi8 : // A8.6.210 T2
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"sub", "\t$Rdn, $imm8",
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[(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
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// subtract register
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def tSUBrr : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
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"sub", "\t$Rd, $Rn, $Rm",
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[(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>,
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T1General<0b01101> {
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// A8.6.212
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bits<3> Rm;
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bits<3> Rn;
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bits<3> Rd;
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let Inst{8-6} = Rm;
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let Inst{5-3} = Rn;
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let Inst{2-0} = Rd;
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}
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// Subtract register
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def tSUBrr : // A8.6.212
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T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iALUr,
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"sub", "\t$Rd, $Rn, $Rm",
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[(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
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// TODO: A7-96: STMIA - store multiple.
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// sign-extend byte
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// Sign-extend byte
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def tSXTB : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
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"sxtb", "\t$Rd, $Rm",
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[(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
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