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Add fastcc cc: pass and return VFP / NEON values in registers. Controlled by -arm-fastcc for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117119 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -52,6 +52,34 @@ def RetCC_ARM_APCS : CallingConv<[
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CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
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]>;
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//===----------------------------------------------------------------------===//
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// ARM APCS Calling Convention for FastCC (when VFP2 or later is available)
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//===----------------------------------------------------------------------===//
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def FastCC_ARM_APCS : CallingConv<[
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// Handle all vector types as either f64 or v2f64.
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
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CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
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CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
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CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
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S9, S10, S11, S12, S13, S14, S15]>>,
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CCDelegateTo<CC_ARM_APCS>
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]>;
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def RetFastCC_ARM_APCS : CallingConv<[
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// Handle all vector types as either f64 or v2f64.
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
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CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
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CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
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CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
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S9, S10, S11, S12, S13, S14, S15]>>,
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CCDelegateTo<RetCC_ARM_APCS>
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]>;
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//===----------------------------------------------------------------------===//
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// ARM AAPCS (EABI) Calling Convention, common parts
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//===----------------------------------------------------------------------===//
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@ -105,6 +133,7 @@ def RetCC_ARM_AAPCS : CallingConv<[
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//===----------------------------------------------------------------------===//
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// ARM AAPCS-VFP (EABI) Calling Convention
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// Also used for FastCC (when VFP2 or later is available)
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//===----------------------------------------------------------------------===//
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def CC_ARM_AAPCS_VFP : CallingConv<[
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@ -69,6 +69,10 @@ ARMInterworking("arm-interworking", cl::Hidden,
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cl::desc("Enable / disable ARM interworking (for debugging only)"),
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cl::init(true));
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static cl::opt<bool>
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ARMFastCC("arm-fastcc", cl::Hidden,
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cl::desc("Use AAPCS / AAPCS-VFP calling conventions for fastcc"));
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void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
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EVT PromotedBitwiseVT) {
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if (VT != PromotedLdStVT) {
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@ -955,23 +959,29 @@ CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
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switch (CC) {
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default:
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llvm_unreachable("Unsupported calling convention");
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case CallingConv::C:
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case CallingConv::Fast:
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if (ARMFastCC && Subtarget->hasVFP2() && !isVarArg) {
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if (!Subtarget->isAAPCS_ABI())
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return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
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// For AAPCS ABI targets, just use VFP variant of the calling convention.
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return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
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}
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// Fallthrough
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case CallingConv::C: {
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// Use target triple & subtarget features to do actual dispatch.
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if (Subtarget->isAAPCS_ABI()) {
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if (Subtarget->hasVFP2() &&
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FloatABIType == FloatABI::Hard && !isVarArg)
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return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
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else
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return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
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} else
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return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
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if (!Subtarget->isAAPCS_ABI())
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return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
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else if (Subtarget->hasVFP2() &&
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FloatABIType == FloatABI::Hard && !isVarArg)
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return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
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return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
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}
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case CallingConv::ARM_AAPCS_VFP:
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return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
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return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
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case CallingConv::ARM_AAPCS:
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return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
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return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
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case CallingConv::ARM_APCS:
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return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
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return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
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}
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}
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