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[X86] Teach how to custom lower double-to-half conversions under fast-math.

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This patch teaches the backend how to expand a double-half conversion into
a double-float conversion immediately followed by a float-half conversion.
We do this only under fast-math, and if float-half conversions are legal
for the target.

Added test CodeGen/X86/fastmath-float-half-conversion.ll

Differential Revision: http://reviews.llvm.org/D7832


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230276 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrea Di Biagio 2015-02-23 22:59:02 +00:00
parent 7ebbc8de2f
commit 770e106ed6
2 changed files with 67 additions and 0 deletions
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15
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -3548,6 +3548,21 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
break;
}
case ISD::FP_TO_FP16: {
if (!TM.Options.UseSoftFloat && TM.Options.UnsafeFPMath) {
SDValue Op = Node->getOperand(0);
MVT SVT = Op.getSimpleValueType();
if ((SVT == MVT::f64 || SVT == MVT::f80) &&
TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) {
// Under fastmath, we can expand this node into a fround followed by
// a float-half conversion.
SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op,
DAG.getIntPtrConstant(0));
Results.push_back(
DAG.getNode(ISD::FP_TO_FP16, dl, MVT::i16, FloatVal));
break;
}
}
RTLIB::Libcall LC =
RTLIB::getFPROUND(Node->getOperand(0).getValueType(), MVT::f16);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to expand fp_to_fp16");

52
test/CodeGen/X86/fastmath-float-half-conversion.ll Normal file
View File

@ -0,0 +1,52 @@
; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+f16c < %s | FileCheck %s --check-prefix=ALL --check-prefix=F16C
; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX
define zeroext i16 @test1_fast(double %d) #0 {
; ALL-LABEL: test1_fast:
; F16C-NOT: callq {{_+}}truncdfhf2
; F16C: vcvtsd2ss %xmm0, %xmm0, %xmm0
; F16C-NEXT: vcvtps2ph $0, %xmm0, %xmm0
; AVX: callq {{_+}}truncdfhf2
; ALL: ret
entry:
%0 = tail call i16 @llvm.convert.to.fp16.f64(double %d)
ret i16 %0
}
define zeroext i16 @test2_fast(x86_fp80 %d) #0 {
; ALL-LABEL: test2_fast:
; F16C-NOT: callq {{_+}}truncxfhf2
; F16C: fldt
; F16C-NEXT: fstps
; F16C-NEXT: vmovss
; F16C-NEXT: vcvtps2ph $0, %xmm0, %xmm0
; AVX: callq {{_+}}truncxfhf2
; ALL: ret
entry:
%0 = tail call i16 @llvm.convert.to.fp16.f80(x86_fp80 %d)
ret i16 %0
}
define zeroext i16 @test1(double %d) #1 {
; ALL-LABEL: test1:
; ALL: callq {{_+}}truncdfhf2
; ALL: ret
entry:
%0 = tail call i16 @llvm.convert.to.fp16.f64(double %d)
ret i16 %0
}
define zeroext i16 @test2(x86_fp80 %d) #1 {
; ALL-LABEL: test2:
; ALL: callq {{_+}}truncxfhf2
; ALL: ret
entry:
%0 = tail call i16 @llvm.convert.to.fp16.f80(x86_fp80 %d)
ret i16 %0
}
declare i16 @llvm.convert.to.fp16.f64(double)
declare i16 @llvm.convert.to.fp16.f80(x86_fp80)
attributes #0 = { nounwind readnone uwtable "unsafe-fp-math"="true" "use-soft-float"="false" }
attributes #1 = { nounwind readnone uwtable "unsafe-fp-math"="false" "use-soft-float"="false" }