6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-18 12:29:27 +00:00
Code Issues Projects Releases Wiki Activity

Fixed features usage.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53277 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2008-07-09 05:32:22 +00:00
parent d1f77bf931
commit 7728f7e890
5 changed files with 25 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
lib/Target/Mips/Mips.td
View File

@ -33,20 +33,22 @@ def MipsInstrInfo : InstrInfo {
// Mips Subtarget features //
//===----------------------------------------------------------------------===//
def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
"General Purpose Registers are 64-bit wide.">;
def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
"Support 64-bit FP registers.">;
def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
"true", "Only supports single precision float">;
def FeatureAllegrexVFPU : SubtargetFeature<"allegrex-vfpu", "HasAllegrexVFPU",
"true", "Enable Allegrex VFPU instructions.">;
def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
"Mips2 ISA Support">;
def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32",
def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32",
"Enable o32 ABI">;
def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI",
def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI",
"Enable eabi ABI">;
def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
"true", "Enable vector FPU instructions.">;
def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true",
"Enable 'signext in register' instructions.">;
//===----------------------------------------------------------------------===//
// Mips processors supported.
@ -64,8 +66,8 @@ def : Proc<"r6000", [FeatureMips2]>;
// Allegrex is a 32bit subset of r4000, both for interger and fp registers,
// but much more similar to Mips2 than Mips3.
def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureAllegrexVFPU,
FeatureEABI]>;
def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureEABI,
FeatureSEInReg, FeatureVFPU]>;
def Mips : Target {
let InstructionSet = MipsInstrInfo;

2
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -122,7 +122,7 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
if (Subtarget->isSingleFloat())
setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
if (!Subtarget->isAllegrex()) {
if (!Subtarget->hasSEInReg()) {
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
}

4
lib/Target/Mips/MipsInstrInfo.td
View File

@ -50,7 +50,7 @@ def MipsSelectCC : SDNode<"MipsISD::SelectCC", SDT_MipsSelectCC>;
//===----------------------------------------------------------------------===//
// Mips Instruction Predicate Definitions.
//===----------------------------------------------------------------------===//
def IsAllegrex : Predicate<"Subtarget.isAllegrex()">;
def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
//===----------------------------------------------------------------------===//
// Mips Operand, Complex Patterns and Transformations Definitions.
@ -510,7 +510,7 @@ def LEA_ADDiu : EffectiveAddress<"addiu $dst, ${addr:stackloc}">;
//def MSUB : MArithR<0x04, "msub">;
//def MSUBU : MArithR<0x05, "msubu">;
let Predicates = [IsAllegrex] in {
let Predicates = [HasSEInReg] in {
let shamt = 0x10, rs = 0 in
def SEB : SignExtInReg<0x21, "seb", i8>;

6
lib/Target/Mips/MipsSubtarget.cpp
View File

@ -20,7 +20,7 @@ using namespace llvm;
MipsSubtarget::MipsSubtarget(const TargetMachine &TM, const Module &M,
const std::string &FS, bool little) :
MipsArchVersion(Mips1), MipsABI(O32), IsLittle(little), IsSingleFloat(false),
IsFP64bit(false), IsGP64bit(false), HasAllegrexVFPU(false), IsAllegrex(false)
IsFP64bit(false), IsGP64bit(false), HasVFPU(false), HasSEInReg(false)
{
std::string CPU = "mips1";
@ -36,7 +36,7 @@ MipsSubtarget::MipsSubtarget(const TargetMachine &TM, const Module &M,
MipsABI = EABI;
IsSingleFloat = true;
MipsArchVersion = Mips2;
HasAllegrexVFPU = true; // Enables Allegrex Vector FPU (not supported yet)
IsAllegrex = true;
HasVFPU = true; // Enables Allegrex Vector FPU (not supported yet)
HasSEInReg = true;
}
}

14
lib/Target/Mips/MipsSubtarget.h
View File

@ -27,7 +27,7 @@ class MipsSubtarget : public TargetSubtarget {
protected:
enum MipsArchEnum {
Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2
Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2, Mips64, Mips64r2
};
enum MipsABIEnum {
@ -54,11 +54,11 @@ protected:
// IsFP64bit - General-purpose registers are 64 bits wide
bool IsGP64bit;
// HasAllegrexVFPU - Allegrex processor has a vector floating point unit.
bool HasAllegrexVFPU;
// HasVFPU - Processor has a vector floating point unit.
bool HasVFPU;
// IsAllegrex - The target processor is a Allegrex core.
bool IsAllegrex;
// HasSEInReg - Target has SEB and SEH (signext in register) instructions.
bool HasSEInReg;
InstrItineraryData InstrItins;
@ -85,8 +85,8 @@ public:
bool isGP32bit() const { return !IsGP64bit; };
bool isSingleFloat() const { return IsSingleFloat; };
bool isNotSingleFloat() const { return !IsSingleFloat; };
bool hasAllegrexVFPU() const { return HasAllegrexVFPU; };
bool isAllegrex() const { return IsAllegrex; };
bool hasVFPU() const { return HasVFPU; };
bool hasSEInReg() const { return HasSEInReg; };
};
} // End llvm namespace