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R600/SI: Initial support for LDS/GDS instructions
Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186009 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -134,6 +134,8 @@ Counters SIInsertWaits::getHwCounts(MachineInstr &MI) {
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if (TSFlags & SIInstrFlags::LGKM_CNT) {
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if (TSFlags & SIInstrFlags::LGKM_CNT) {
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MachineOperand &Op = MI.getOperand(0);
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MachineOperand &Op = MI.getOperand(0);
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if (!Op.isReg())
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Op = MI.getOperand(1);
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assert(Op.isReg() && "First LGKM operand must be a register!");
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assert(Op.isReg() && "First LGKM operand must be a register!");
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unsigned Reg = Op.getReg();
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unsigned Reg = Op.getReg();
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@ -281,6 +281,30 @@ class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
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let Uses = [EXEC] in {
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let Uses = [EXEC] in {
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class DS <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc64 <outs, ins, asm, pattern> {
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bits<8> vdst;
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bits<1> gds;
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bits<8> addr;
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bits<8> data0;
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bits<8> data1;
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bits<8> offset0;
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bits<8> offset1;
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let Inst{7-0} = offset0;
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let Inst{15-8} = offset1;
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let Inst{17} = gds;
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let Inst{25-18} = op;
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let Inst{31-26} = 0x36; //encoding
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let Inst{39-32} = addr;
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let Inst{47-40} = data0;
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let Inst{55-48} = data1;
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let Inst{63-56} = vdst;
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let LGKM_CNT = 1;
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}
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class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc64<outs, ins, asm, pattern> {
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Enc64<outs, ins, asm, pattern> {
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@ -287,6 +287,29 @@ class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
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// Vector I/O classes
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// Vector I/O classes
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
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op,
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(outs regClass:$vdst),
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(ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, VReg_32:$data1,
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i8imm:$offset0, i8imm:$offset1),
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asm#" $vdst, $gds, $addr, $data0, $data1, $offset0, $offset1, [M0]",
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[]> {
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let mayLoad = 1;
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let mayStore = 0;
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}
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class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
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op,
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(outs),
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(ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, VReg_32:$data1,
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i8imm:$offset0, i8imm:$offset1),
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asm#" $gds, $addr, $data0, $data1, $offset0, $offset1, [M0]",
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[]> {
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let mayStore = 1;
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let mayLoad = 0;
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let vdst = 0;
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}
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class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
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class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
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op,
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op,
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(outs),
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(outs),
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@ -391,6 +391,9 @@ defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">;
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} // End isCompare = 1
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} // End isCompare = 1
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def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>;
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def DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>;
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//def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>;
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//def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>;
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//def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>;
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//def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>;
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//def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>;
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//def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>;
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@ -411,6 +411,7 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
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TRI = MF.getTarget().getRegisterInfo();
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TRI = MF.getTarget().getRegisterInfo();
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bool HaveKill = false;
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bool HaveKill = false;
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bool NeedM0 = false;
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bool NeedWQM = false;
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bool NeedWQM = false;
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unsigned Depth = 0;
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unsigned Depth = 0;
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@ -482,6 +483,13 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
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IndirectDst(MI);
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IndirectDst(MI);
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break;
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break;
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case AMDGPU::DS_READ_B32:
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NeedWQM = true;
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// Fall through
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case AMDGPU::DS_WRITE_B32:
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NeedM0 = true;
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break;
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case AMDGPU::V_INTERP_P1_F32:
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case AMDGPU::V_INTERP_P1_F32:
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case AMDGPU::V_INTERP_P2_F32:
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case AMDGPU::V_INTERP_P2_F32:
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case AMDGPU::V_INTERP_MOV_F32:
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case AMDGPU::V_INTERP_MOV_F32:
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@ -492,6 +500,14 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
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}
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}
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}
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}
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if (NeedM0) {
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MachineBasicBlock &MBB = MF.front();
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// Initialize M0 to a value that won't cause LDS access to be discarded
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// due to offset clamping
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BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_MOV_B32),
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AMDGPU::M0).addImm(0xffffffff);
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}
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if (NeedWQM) {
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if (NeedWQM) {
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MachineBasicBlock &MBB = MF.front();
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MachineBasicBlock &MBB = MF.front();
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BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_WQM_B64),
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BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_WQM_B64),
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