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Enhance address-mode folding of ISD::ADD to handle cases where the
operands can't both be fully folded at the same time. For example, in the included testcase, a global variable is being added with an add of two values. The global variable wants RIP-relative addressing, so it can't share the address with another base register, but it's still possible to fold the initial add. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66865 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -907,6 +907,19 @@ bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM,
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!MatchAddress(N.getNode()->getOperand(0), AM, false, Depth+1))
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return false;
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AM = Backup;
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// If we couldn't fold both operands into the address at the same time,
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// see if we can just put each operand into a register and fold at least
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// the add.
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if (AM.BaseType == X86ISelAddressMode::RegBase &&
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!AM.Base.Reg.getNode() &&
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!AM.IndexReg.getNode() &&
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!AM.isRIPRel) {
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AM.Base.Reg = N.getNode()->getOperand(0);
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AM.IndexReg = N.getNode()->getOperand(1);
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AM.Scale = 1;
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return false;
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}
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break;
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}
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25
test/CodeGen/X86/fold-add.ll
Normal file
25
test/CodeGen/X86/fold-add.ll
Normal file
@ -0,0 +1,25 @@
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; RUN: llvm-as < %s | llc -march=x86-64 | grep {cmpb \$0, (%r.\*,%r.\*)}
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
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target triple = "x86_64-apple-darwin9.6"
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@prev_length = internal global i32 0 ; <i32*> [#uses=1]
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@window = internal global [65536 x i8] zeroinitializer, align 32 ; <[65536 x i8]*> [#uses=1]
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@llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (i32)* @longest_match to i8*)] ; <[1 x i8*]*> [#uses=0]
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define fastcc i32 @longest_match(i32 %cur_match) nounwind {
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entry:
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%0 = load i32* @prev_length, align 4 ; <i32> [#uses=3]
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%1 = zext i32 %cur_match to i64 ; <i64> [#uses=1]
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%2 = sext i32 %0 to i64 ; <i64> [#uses=1]
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%.sum3 = add i64 %1, %2 ; <i64> [#uses=1]
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%3 = getelementptr [65536 x i8]* @window, i64 0, i64 %.sum3 ; <i8*> [#uses=1]
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%4 = load i8* %3, align 1 ; <i8> [#uses=1]
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%5 = icmp eq i8 %4, 0 ; <i1> [#uses=1]
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br i1 %5, label %bb5, label %bb23
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bb5: ; preds = %entry
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ret i32 %0
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bb23: ; preds = %entry
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ret i32 %0
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}
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