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[PowerPC] Don't attempt a 64-bit pow2 division on PPC32

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In r224033, in moving the signed power-of-2 division expansion into
BuildSDIVPow2, I accidentally made it possible to attempt the lowering for a
64-bit division on PPC32. This later asserts.

Fixes PR21928.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224758 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2014-12-23 08:38:50 +00:00
parent b9e302f3ca
commit 775294d183
2 changed files with 11 additions and 0 deletions
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2
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -8966,6 +8966,8 @@ PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
std::vector<SDNode *> *Created) const {
// fold (sdiv X, pow2)
EVT VT = N->getValueType(0);
if (VT == MVT::i64 && !Subtarget.isPPC64())
return SDValue();
if ((VT != MVT::i32 && VT != MVT::i64) ||
!(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
return SDValue();

9
test/CodeGen/PowerPC/sdiv-pow2.ll
View File

@ -1,4 +1,5 @@
; RUN: llc -mcpu=ppc64 < %s | FileCheck %s
; RUN: llc -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc < %s | FileCheck -check-prefix=CHECK-32 %s
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
@ -25,6 +26,10 @@ entry:
; CHECK: sradi [[REG1:[0-9]+]], 3, 3
; CHECK: addze 3, [[REG1]]
; CHECK: blr
; CHECK-32-LABEL @foo8
; CHECK-32-NOT: sradi
; CHECK-32: blr
}
; Function Attrs: nounwind readnone
@ -52,6 +57,10 @@ entry:
; CHECK: addze [[REG2:[0-9]+]], [[REG1]]
; CHECK: neg 3, [[REG2]]
; CHECK: blr
; CHECK-32-LABEL @foo8n
; CHECK-32-NOT: sradi
; CHECK-32: blr
}
attributes #0 = { nounwind readnone }