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Revert "Combine bit test + conditional or into simple math"
It is causing stage2 builds to fail, let's get them running again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179750 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -350,64 +350,6 @@ static Value *SimplifyWithOpReplaced(Value *V, Value *Op, Value *RepOp,
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return 0;
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}
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/// foldSelectICmpAndOr - We want to turn:
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/// (select (icmp eq (and X, C1), 0), Y, (or Y, C2))
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/// into:
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/// (or (shl (and X, C1), C3), y)
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/// iff:
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/// C1 and C2 are both powers of 2
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/// where:
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/// C3 = Log(C2) - Log(C1)
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///
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/// This transform handles cases where:
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/// 1. The icmp predicate is inverted
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/// 2. The select operands are reversed
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/// 3. The magnitude of C2 and C1 are flipped
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static Value *foldSelectICmpAndOr(const SelectInst &SI, Value *TrueVal,
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Value *FalseVal,
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InstCombiner::BuilderTy *Builder) {
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const ICmpInst *IC = dyn_cast<ICmpInst>(SI.getCondition());
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if (!IC || !IC->isEquality())
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return 0;
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Value *CmpLHS = IC->getOperand(0);
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Value *CmpRHS = IC->getOperand(1);
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if (!match(CmpRHS, m_Zero()))
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return 0;
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Value *X;
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const APInt *C1;
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if (!match(CmpLHS, m_And(m_Value(X), m_Power2(C1))))
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return 0;
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const APInt *C2;
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bool OrOnTrueVal = false;
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bool OrOnFalseVal = match(FalseVal, m_Or(m_Specific(TrueVal), m_Power2(C2)));
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if (!OrOnFalseVal)
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OrOnTrueVal = match(TrueVal, m_Or(m_Specific(FalseVal), m_Power2(C2)));
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if (!OrOnFalseVal && !OrOnTrueVal)
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return 0;
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Value *V = CmpLHS;
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unsigned C1Log = C1->logBase2();
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unsigned C2Log = C2->logBase2();
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if (C2Log > C1Log)
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V = Builder->CreateShl(V, C2Log - C1Log);
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else if (C1Log > C2Log)
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V = Builder->CreateLShr(V, C1Log - C2Log);
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ICmpInst::Predicate Pred = IC->getPredicate();
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if ((Pred == ICmpInst::ICMP_NE && OrOnFalseVal) ||
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(Pred == ICmpInst::ICMP_EQ && OrOnTrueVal))
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V = Builder->CreateXor(V, *C2);
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Value *Y = OrOnFalseVal ? TrueVal : FalseVal;
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return Builder->CreateOr(V, Y);
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}
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/// visitSelectInstWithICmp - Visit a SelectInst that has an
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/// ICmpInst as its first operand.
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///
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@ -579,9 +521,6 @@ Instruction *InstCombiner::visitSelectInstWithICmp(SelectInst &SI,
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}
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}
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if (Value *V = foldSelectICmpAndOr(SI, TrueVal, FalseVal, Builder))
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return ReplaceInstUsesWith(SI, V);
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return Changed ? &SI : 0;
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}
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@ -863,82 +863,3 @@ while.body:
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; CHECK: @test64
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; CHECK-NOT: select
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}
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; CHECK: @select_icmp_eq_and_1_0_or_2
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; CHECK-NEXT: [[SHL:%[a-z0-9]+]] = shl i32 %x, 1
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; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[SHL]], 2
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; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[AND]], %y
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; CHECK-NEXT: ret i32 [[OR]]
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define i32 @select_icmp_eq_and_1_0_or_2(i32 %x, i32 %y) {
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%and = and i32 %x, 1
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%cmp = icmp eq i32 %and, 0
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%or = or i32 %y, 2
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%select = select i1 %cmp, i32 %y, i32 %or
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ret i32 %select
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}
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; CHECK: @select_icmp_eq_and_32_0_or_8
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; CHECK-NEXT: [[LSHR:%[a-z0-9]+]] = lshr i32 %x, 2
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; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[LSHR]], 8
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; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[AND]], %y
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; CHECK-NEXT: ret i32 [[OR]]
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define i32 @select_icmp_eq_and_32_0_or_8(i32 %x, i32 %y) {
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%and = and i32 %x, 32
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%cmp = icmp eq i32 %and, 0
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%or = or i32 %y, 8
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%select = select i1 %cmp, i32 %y, i32 %or
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ret i32 %select
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}
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; CHECK: @select_icmp_ne_0_and_4096_or_4096
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; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %x, 4096
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; CHECK-NEXT: [[XOR:%[a-z0-9]+]] = xor i32 [[AND]], 4096
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; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[XOR]], %y
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; CHECK-NEXT: ret i32 [[OR]]
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define i32 @select_icmp_ne_0_and_4096_or_4096(i32 %x, i32 %y) {
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%and = and i32 %x, 4096
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%cmp = icmp ne i32 0, %and
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%or = or i32 %y, 4096
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%select = select i1 %cmp, i32 %y, i32 %or
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ret i32 %select
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}
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; CHECK: @select_icmp_eq_and_4096_0_or_4096
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; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %x, 4096
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; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[AND]], %y
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; CHECK-NEXT: ret i32 [[OR]]
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define i32 @select_icmp_eq_and_4096_0_or_4096(i32 %x, i32 %y) {
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%and = and i32 %x, 4096
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%cmp = icmp eq i32 %and, 0
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%or = or i32 %y, 4096
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%select = select i1 %cmp, i32 %y, i32 %or
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ret i32 %select
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}
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; CHECK: @select_icmp_ne_0_and_4096_or_32
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; CHECK-NEXT: [[LSHR:%[a-z0-9]+]] = lshr i32 %x, 7
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; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[LSHR]], 32
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; CHECK-NEXT: [[XOR:%[a-z0-9]+]] = xor i32 [[AND]], 32
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; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[XOR]], %y
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; CHECK-NEXT: ret i32 [[OR]]
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define i32 @select_icmp_ne_0_and_4096_or_32(i32 %x, i32 %y) {
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%and = and i32 %x, 4096
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%cmp = icmp ne i32 0, %and
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%or = or i32 %y, 32
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%select = select i1 %cmp, i32 %y, i32 %or
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ret i32 %select
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}
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; CHECK: @select_icmp_ne_0_and_32_or_4096
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; CHECK-NEXT: [[SHL:%[a-z0-9]+]] = shl i32 %x, 7
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; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[SHL]], 4096
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; CHECK-NEXT: [[XOR:%[a-z0-9]+]] = xor i32 [[AND]], 4096
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; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[XOR]], %y
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; CHECK-NEXT: ret i32 [[OR]]
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define i32 @select_icmp_ne_0_and_32_or_4096(i32 %x, i32 %y) {
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%and = and i32 %x, 32
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%cmp = icmp ne i32 0, %and
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%or = or i32 %y, 4096
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%select = select i1 %cmp, i32 %y, i32 %or
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ret i32 %select
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}
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