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Revert "Combine bit test + conditional or into simple math"

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It is causing stage2 builds to fail, let's get them running again.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179750 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Majnemer 2013-04-18 08:42:33 +00:00
parent a40a3a5981
commit 7754276c4c
2 changed files with 0 additions and 140 deletions
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61
lib/Transforms/InstCombine/InstCombineSelect.cpp
View File

@ -350,64 +350,6 @@ static Value *SimplifyWithOpReplaced(Value *V, Value *Op, Value *RepOp,
return 0;
}
/// foldSelectICmpAndOr - We want to turn:
/// (select (icmp eq (and X, C1), 0), Y, (or Y, C2))
/// into:
/// (or (shl (and X, C1), C3), y)
/// iff:
/// C1 and C2 are both powers of 2
/// where:
/// C3 = Log(C2) - Log(C1)
///
/// This transform handles cases where:
/// 1. The icmp predicate is inverted
/// 2. The select operands are reversed
/// 3. The magnitude of C2 and C1 are flipped
static Value *foldSelectICmpAndOr(const SelectInst &SI, Value *TrueVal,
Value *FalseVal,
InstCombiner::BuilderTy *Builder) {
const ICmpInst *IC = dyn_cast<ICmpInst>(SI.getCondition());
if (!IC || !IC->isEquality())
return 0;
Value *CmpLHS = IC->getOperand(0);
Value *CmpRHS = IC->getOperand(1);
if (!match(CmpRHS, m_Zero()))
return 0;
Value *X;
const APInt *C1;
if (!match(CmpLHS, m_And(m_Value(X), m_Power2(C1))))
return 0;
const APInt *C2;
bool OrOnTrueVal = false;
bool OrOnFalseVal = match(FalseVal, m_Or(m_Specific(TrueVal), m_Power2(C2)));
if (!OrOnFalseVal)
OrOnTrueVal = match(TrueVal, m_Or(m_Specific(FalseVal), m_Power2(C2)));
if (!OrOnFalseVal && !OrOnTrueVal)
return 0;
Value *V = CmpLHS;
unsigned C1Log = C1->logBase2();
unsigned C2Log = C2->logBase2();
if (C2Log > C1Log)
V = Builder->CreateShl(V, C2Log - C1Log);
else if (C1Log > C2Log)
V = Builder->CreateLShr(V, C1Log - C2Log);
ICmpInst::Predicate Pred = IC->getPredicate();
if ((Pred == ICmpInst::ICMP_NE && OrOnFalseVal) ||
(Pred == ICmpInst::ICMP_EQ && OrOnTrueVal))
V = Builder->CreateXor(V, *C2);
Value *Y = OrOnFalseVal ? TrueVal : FalseVal;
return Builder->CreateOr(V, Y);
}
/// visitSelectInstWithICmp - Visit a SelectInst that has an
/// ICmpInst as its first operand.
///
@ -579,9 +521,6 @@ Instruction *InstCombiner::visitSelectInstWithICmp(SelectInst &SI,
}
}
if (Value *V = foldSelectICmpAndOr(SI, TrueVal, FalseVal, Builder))
return ReplaceInstUsesWith(SI, V);
return Changed ? &SI : 0;
}

79
test/Transforms/InstCombine/select.ll
View File

@ -863,82 +863,3 @@ while.body:
; CHECK: @test64
; CHECK-NOT: select
}
; CHECK: @select_icmp_eq_and_1_0_or_2
; CHECK-NEXT: [[SHL:%[a-z0-9]+]] = shl i32 %x, 1
; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[SHL]], 2
; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[AND]], %y
; CHECK-NEXT: ret i32 [[OR]]
define i32 @select_icmp_eq_and_1_0_or_2(i32 %x, i32 %y) {
%and = and i32 %x, 1
%cmp = icmp eq i32 %and, 0
%or = or i32 %y, 2
%select = select i1 %cmp, i32 %y, i32 %or
ret i32 %select
}
; CHECK: @select_icmp_eq_and_32_0_or_8
; CHECK-NEXT: [[LSHR:%[a-z0-9]+]] = lshr i32 %x, 2
; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[LSHR]], 8
; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[AND]], %y
; CHECK-NEXT: ret i32 [[OR]]
define i32 @select_icmp_eq_and_32_0_or_8(i32 %x, i32 %y) {
%and = and i32 %x, 32
%cmp = icmp eq i32 %and, 0
%or = or i32 %y, 8
%select = select i1 %cmp, i32 %y, i32 %or
ret i32 %select
}
; CHECK: @select_icmp_ne_0_and_4096_or_4096
; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %x, 4096
; CHECK-NEXT: [[XOR:%[a-z0-9]+]] = xor i32 [[AND]], 4096
; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[XOR]], %y
; CHECK-NEXT: ret i32 [[OR]]
define i32 @select_icmp_ne_0_and_4096_or_4096(i32 %x, i32 %y) {
%and = and i32 %x, 4096
%cmp = icmp ne i32 0, %and
%or = or i32 %y, 4096
%select = select i1 %cmp, i32 %y, i32 %or
ret i32 %select
}
; CHECK: @select_icmp_eq_and_4096_0_or_4096
; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %x, 4096
; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[AND]], %y
; CHECK-NEXT: ret i32 [[OR]]
define i32 @select_icmp_eq_and_4096_0_or_4096(i32 %x, i32 %y) {
%and = and i32 %x, 4096
%cmp = icmp eq i32 %and, 0
%or = or i32 %y, 4096
%select = select i1 %cmp, i32 %y, i32 %or
ret i32 %select
}
; CHECK: @select_icmp_ne_0_and_4096_or_32
; CHECK-NEXT: [[LSHR:%[a-z0-9]+]] = lshr i32 %x, 7
; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[LSHR]], 32
; CHECK-NEXT: [[XOR:%[a-z0-9]+]] = xor i32 [[AND]], 32
; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[XOR]], %y
; CHECK-NEXT: ret i32 [[OR]]
define i32 @select_icmp_ne_0_and_4096_or_32(i32 %x, i32 %y) {
%and = and i32 %x, 4096
%cmp = icmp ne i32 0, %and
%or = or i32 %y, 32
%select = select i1 %cmp, i32 %y, i32 %or
ret i32 %select
}
; CHECK: @select_icmp_ne_0_and_32_or_4096
; CHECK-NEXT: [[SHL:%[a-z0-9]+]] = shl i32 %x, 7
; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[SHL]], 4096
; CHECK-NEXT: [[XOR:%[a-z0-9]+]] = xor i32 [[AND]], 4096
; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[XOR]], %y
; CHECK-NEXT: ret i32 [[OR]]
define i32 @select_icmp_ne_0_and_32_or_4096(i32 %x, i32 %y) {
%and = and i32 %x, 32
%cmp = icmp ne i32 0, %and
%or = or i32 %y, 4096
%select = select i1 %cmp, i32 %y, i32 %or
ret i32 %select
}