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Teach DAGISelEmitter about zero_reg.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37900 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-07-05 07:19:45 +00:00
parent 8012b077dd
commit 7774be4a74
1 changed files with 8 additions and 1 deletions
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9
utils/TableGen/DAGISelEmitter.cpp
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@ -622,7 +622,8 @@ static std::vector<unsigned char> getImplicitType(Record *R, bool NotRegisters,
} else if (R->getName() == "ptr_rc") { } else if (R->getName() == "ptr_rc") {
Other[0] = MVT::iPTR; Other[0] = MVT::iPTR;
return Other; return Other;
} else if (R->getName() == "node" || R->getName() == "srcvalue") { } else if (R->getName() == "node" || R->getName() == "srcvalue" ||
R->getName() == "zero_reg") {
// Placeholder. // Placeholder.
return Unknown; return Unknown;
} }
@ -2711,6 +2712,12 @@ public:
getEnumName(N->getTypeNum(0)) + ");"); getEnumName(N->getTypeNum(0)) + ");");
NodeOps.push_back("Tmp" + utostr(ResNo)); NodeOps.push_back("Tmp" + utostr(ResNo));
return NodeOps; return NodeOps;
} else if (DI->getDef()->getName() == "zero_reg") {
emitCode("SDOperand Tmp" + utostr(ResNo) +
" = CurDAG->getRegister(0, " +
getEnumName(N->getTypeNum(0)) + ");");
NodeOps.push_back("Tmp" + utostr(ResNo));
return NodeOps;
} }
} else if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) { } else if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) {
unsigned ResNo = TmpNo++; unsigned ResNo = TmpNo++;