diff --git a/lib/Target/R600/AMDGPUAsmPrinter.cpp b/lib/Target/R600/AMDGPUAsmPrinter.cpp index 1a0a7db9b1c..5511d7c6f8f 100644 --- a/lib/Target/R600/AMDGPUAsmPrinter.cpp +++ b/lib/Target/R600/AMDGPUAsmPrinter.cpp @@ -97,6 +97,10 @@ void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) { } bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) { + + // The starting address of all shader programs must be 256 bytes aligned. + MF.setAlignment(8); + SetupMachineFunction(MF); EmitFunctionHeader(); diff --git a/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp b/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp index d55f27b0455..5fb311b3016 100644 --- a/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp +++ b/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp @@ -57,9 +57,7 @@ public: assert(!"Not implemented"); } bool mayNeedRelaxation(const MCInst &Inst) const override { return false; } - bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override { - return true; - } + bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override; const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override; }; @@ -116,6 +114,13 @@ const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo( return Infos[Kind - FirstTargetFixupKind]; } +bool AMDGPUAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { + for (unsigned i = 0; i < Count; ++i) + OW->Write8(0); + + return true; +} + //===----------------------------------------------------------------------===// // ELFAMDGPUAsmBackend class //===----------------------------------------------------------------------===// diff --git a/test/CodeGen/R600/elf.ll b/test/CodeGen/R600/elf.ll index 93851504bd4..6c521d0957c 100644 --- a/test/CodeGen/R600/elf.ll +++ b/test/CodeGen/R600/elf.ll @@ -5,6 +5,8 @@ ; ELF-CHECK: Name: .AMDGPU.config ; ELF-CHECK: Type: SHT_PROGBITS +; CONFIG-CHECK: .align 256 +; CONFIG-CHECK: test: ; CONFIG-CHECK: .section .AMDGPU.config ; CONFIG-CHECK-NEXT: .long 45096 ; CONFIG-CHECK-NEXT: .long 0