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Fix the order of the operands in the llvm.fma intrinsic patterns for ARM,
<rdar://problem/11325085>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155724 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -4136,16 +4136,16 @@ def VFMSfq : N3VQMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACQ, "vfms", "f32",
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Requires<[HasVFP4,UseFusedMAC]>;
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Requires<[HasVFP4,UseFusedMAC]>;
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// Match @llvm.fma.* intrinsics
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// Match @llvm.fma.* intrinsics
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def : Pat<(v2f32 (fma DPR:$src1, DPR:$Vn, DPR:$Vm)),
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def : Pat<(v2f32 (fma DPR:$Vn, DPR:$Vm, DPR:$src1)),
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(VFMAfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
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(VFMAfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
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Requires<[HasVFP4]>;
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Requires<[HasVFP4]>;
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def : Pat<(v4f32 (fma QPR:$src1, QPR:$Vn, QPR:$Vm)),
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def : Pat<(v4f32 (fma QPR:$Vn, QPR:$Vm, QPR:$src1)),
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(VFMAfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
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(VFMAfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
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Requires<[HasVFP4]>;
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Requires<[HasVFP4]>;
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def : Pat<(v2f32 (fma (fneg DPR:$src1), DPR:$Vn, DPR:$Vm)),
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def : Pat<(v2f32 (fma (fneg DPR:$Vn), DPR:$Vm, DPR:$src1)),
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(VFMSfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
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(VFMSfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
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Requires<[HasVFP4]>;
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Requires<[HasVFP4]>;
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def : Pat<(v4f32 (fma (fneg QPR:$src1), QPR:$Vn, QPR:$Vm)),
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def : Pat<(v4f32 (fma (fneg QPR:$Vn), QPR:$Vm, QPR:$src1)),
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(VFMSfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
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(VFMSfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
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Requires<[HasVFP4]>;
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Requires<[HasVFP4]>;
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@ -1089,10 +1089,11 @@ def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
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Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
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Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
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// Match @llvm.fma.* intrinsics
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// Match @llvm.fma.* intrinsics
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def : Pat<(f64 (fma DPR:$Ddin, DPR:$Dn, DPR:$Dm)),
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// (fma x, y, z) -> (vfms z, x, y)
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def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)),
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(VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
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(VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
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Requires<[HasVFP4]>;
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Requires<[HasVFP4]>;
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def : Pat<(f32 (fma SPR:$Sdin, SPR:$Sn, SPR:$Sm)),
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def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)),
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(VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
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(VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
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Requires<[HasVFP4]>;
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Requires<[HasVFP4]>;
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@ -1123,18 +1124,18 @@ def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
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Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
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Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
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// Match @llvm.fma.* intrinsics
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// Match @llvm.fma.* intrinsics
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// (fma (fneg x), y, z) -> (vfms x, y, z)
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// (fma (fneg x), y, z) -> (vfms z, x, y)
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def : Pat<(f64 (fma (fneg DPR:$Ddin), DPR:$Dn, DPR:$Dm)),
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def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)),
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(VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
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(VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
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Requires<[HasVFP4]>;
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Requires<[HasVFP4]>;
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def : Pat<(f32 (fma (fneg SPR:$Sdin), SPR:$Sn, SPR:$Sm)),
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def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
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(VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
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(VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
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Requires<[HasVFP4]>;
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Requires<[HasVFP4]>;
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// (fneg (fma x, (fneg y), z) -> (vfms x, y, z)
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// (fma x, (fneg y), z) -> (vfms z, x, y)
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def : Pat<(fneg (f64 (fma DPR:$Ddin, (fneg DPR:$Dn), DPR:$Dm))),
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def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)),
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(VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
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(VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
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Requires<[HasVFP4]>;
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Requires<[HasVFP4]>;
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def : Pat<(fneg (f32 (fma SPR:$Sdin, (fneg SPR:$Sn), SPR:$Sm))),
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def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)),
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(VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
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(VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
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Requires<[HasVFP4]>;
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Requires<[HasVFP4]>;
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@ -1165,18 +1166,18 @@ def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
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Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
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Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
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// Match @llvm.fma.* intrinsics
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// Match @llvm.fma.* intrinsics
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// (fneg (fma x, y, z)) -> (vfnma x, y, z)
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// (fneg (fma x, y, z)) -> (vfnma z, x, y)
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def : Pat<(fneg (fma (f64 DPR:$Ddin), (f64 DPR:$Dn), (f64 DPR:$Dm))),
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def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))),
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(VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
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(VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
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Requires<[HasVFP4]>;
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Requires<[HasVFP4]>;
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def : Pat<(fneg (fma (f32 SPR:$Sdin), (f32 SPR:$Sn), (f32 SPR:$Sm))),
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def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))),
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(VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
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(VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
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Requires<[HasVFP4]>;
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Requires<[HasVFP4]>;
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// (fma (fneg x), y, (fneg z)) -> (vfnma x, y, z)
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// (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y)
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def : Pat<(f64 (fma (fneg DPR:$Ddin), DPR:$Dn, (fneg DPR:$Dm))),
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def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))),
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(VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
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(VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
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Requires<[HasVFP4]>;
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Requires<[HasVFP4]>;
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def : Pat<(f32 (fma (fneg SPR:$Sdin), SPR:$Sn, (fneg SPR:$Sm))),
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def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))),
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(VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
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(VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
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Requires<[HasVFP4]>;
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Requires<[HasVFP4]>;
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@ -1206,18 +1207,18 @@ def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
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Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
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Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
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// Match @llvm.fma.* intrinsics
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// Match @llvm.fma.* intrinsics
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// (fneg (fma (fneg x), y, z)) -> (vnfms x, y, z)
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// (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y)
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def : Pat<(fneg (f64 (fma (fneg DPR:$Ddin), DPR:$Dn, DPR:$Dm))),
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def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))),
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(VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
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(VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
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Requires<[HasVFP4]>;
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Requires<[HasVFP4]>;
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def : Pat<(fneg (f32 (fma (fneg SPR:$Sdin), SPR:$Sn, SPR:$Sm))),
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def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))),
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(VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
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(VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
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Requires<[HasVFP4]>;
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Requires<[HasVFP4]>;
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// (fma x, (fneg y), z) -> (vnfms x, y, z)
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// (fneg (fma x, (fneg y), z) -> (vfnms z, x, y)
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def : Pat<(f64 (fma DPR:$Ddin, (fneg DPR:$Dn), DPR:$Dm)),
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def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))),
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(VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
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(VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
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Requires<[HasVFP4]>;
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Requires<[HasVFP4]>;
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def : Pat<(f32 (fma SPR:$Sdin, (fneg SPR:$Sn), SPR:$Sm)),
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def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))),
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(VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
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(VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
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Requires<[HasVFP4]>;
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Requires<[HasVFP4]>;
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@ -138,8 +138,7 @@ entry:
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; CHECK: vfms.f64
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; CHECK: vfms.f64
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%tmp1 = fsub double -0.0, %b
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%tmp1 = fsub double -0.0, %b
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%tmp2 = tail call double @llvm.fma.f64(double %a, double %tmp1, double %c) nounwind readnone
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%tmp2 = tail call double @llvm.fma.f64(double %a, double %tmp1, double %c) nounwind readnone
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%tmp3 = fsub double -0.0, %tmp2
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ret double %tmp2
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ret double %tmp3
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}
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}
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define double @test_fnms_f64(double %a, double %b, double %c) nounwind readnone ssp {
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define double @test_fnms_f64(double %a, double %b, double %c) nounwind readnone ssp {
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@ -158,7 +157,8 @@ entry:
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; CHECK: vfnms.f64
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; CHECK: vfnms.f64
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%tmp1 = fsub double -0.0, %b
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%tmp1 = fsub double -0.0, %b
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%tmp2 = tail call double @llvm.fma.f64(double %a, double %tmp1, double %c) nounwind readnone
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%tmp2 = tail call double @llvm.fma.f64(double %a, double %tmp1, double %c) nounwind readnone
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ret double %tmp2
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%tmp3 = fsub double -0.0, %tmp2
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ret double %tmp3
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}
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}
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define double @test_fnma_f64(double %a, double %b, double %c) nounwind readnone ssp {
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define double @test_fnma_f64(double %a, double %b, double %c) nounwind readnone ssp {
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