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Add intrinsics for log, log2, log10, exp, exp2.

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No functional change (and no FE change to generate them).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55753 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen
2008-09-04 00:47:13 +00:00
parent 104e4ce162
commit 7794f2a3a7
14 changed files with 438 additions and 1 deletions
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70
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@@ -3490,6 +3490,11 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
case ISD::FSQRT:
case ISD::FSIN:
case ISD::FCOS:
case ISD::FLOG:
case ISD::FLOG2:
case ISD::FLOG10:
case ISD::FEXP:
case ISD::FEXP2:
case ISD::FTRUNC:
case ISD::FFLOOR:
case ISD::FCEIL:
@@ -3526,6 +3531,11 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
break;
}
case ISD::FLOG:
case ISD::FLOG2:
case ISD::FLOG10:
case ISD::FEXP:
case ISD::FEXP2:
case ISD::FTRUNC:
case ISD::FFLOOR:
case ISD::FCEIL:
@@ -3556,6 +3566,26 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
RTLIB::COS_F80, RTLIB::COS_PPCF128);
break;
case ISD::FLOG:
LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
break;
case ISD::FLOG2:
LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
break;
case ISD::FLOG10:
LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
break;
case ISD::FEXP:
LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
break;
case ISD::FEXP2:
LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
break;
case ISD::FTRUNC:
LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
@@ -4163,6 +4193,11 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
// precision, and these operations don't modify precision at all.
break;
case ISD::FLOG:
case ISD::FLOG2:
case ISD::FLOG10:
case ISD::FEXP:
case ISD::FEXP2:
case ISD::FSQRT:
case ISD::FSIN:
case ISD::FCOS:
@@ -6574,6 +6609,11 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
RTLIB::POWI_PPCF128),
Node, false, Hi);
break;
case ISD::FLOG:
case ISD::FLOG2:
case ISD::FLOG10:
case ISD::FEXP:
case ISD::FEXP2:
case ISD::FTRUNC:
case ISD::FFLOOR:
case ISD::FCEIL:
@@ -6596,6 +6636,26 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
RTLIB::COS_F80, RTLIB::COS_PPCF128);
break;
case ISD::FLOG:
LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
break;
case ISD::FLOG2:
LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
break;
case ISD::FLOG10:
LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
break;
case ISD::FEXP:
LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
break;
case ISD::FEXP2:
LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
break;
case ISD::FTRUNC:
LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
@@ -6966,6 +7026,11 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
case ISD::FSQRT:
case ISD::FSIN:
case ISD::FCOS:
case ISD::FLOG:
case ISD::FLOG2:
case ISD::FLOG10:
case ISD::FEXP:
case ISD::FEXP2:
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT:
case ISD::SINT_TO_FP:
@@ -7102,6 +7167,11 @@ SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
case ISD::FSQRT:
case ISD::FSIN:
case ISD::FCOS:
case ISD::FLOG:
case ISD::FLOG2:
case ISD::FLOG10:
case ISD::FEXP:
case ISD::FEXP2:
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT:
case ISD::SINT_TO_FP:

25
lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
View File

@@ -3015,6 +3015,31 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
getValue(I.getOperand(1)).getValueType(),
getValue(I.getOperand(1))));
return 0;
case Intrinsic::log:
setValue(&I, DAG.getNode(ISD::FLOG,
getValue(I.getOperand(1)).getValueType(),
getValue(I.getOperand(1))));
return 0;
case Intrinsic::log2:
setValue(&I, DAG.getNode(ISD::FLOG2,
getValue(I.getOperand(1)).getValueType(),
getValue(I.getOperand(1))));
return 0;
case Intrinsic::log10:
setValue(&I, DAG.getNode(ISD::FLOG10,
getValue(I.getOperand(1)).getValueType(),
getValue(I.getOperand(1))));
return 0;
case Intrinsic::exp:
setValue(&I, DAG.getNode(ISD::FEXP,
getValue(I.getOperand(1)).getValueType(),
getValue(I.getOperand(1))));
return 0;
case Intrinsic::exp2:
setValue(&I, DAG.getNode(ISD::FEXP2,
getValue(I.getOperand(1)).getValueType(),
getValue(I.getOperand(1))));
return 0;
case Intrinsic::pow:
setValue(&I, DAG.getNode(ISD::FPOW,
getValue(I.getOperand(1)).getValueType(),

20
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@@ -83,6 +83,26 @@ static void InitLibcallNames(const char **Names) {
Names[RTLIB::SQRT_F64] = "sqrt";
Names[RTLIB::SQRT_F80] = "sqrtl";
Names[RTLIB::SQRT_PPCF128] = "sqrtl";
Names[RTLIB::LOG_F32] = "logf";
Names[RTLIB::LOG_F64] = "log";
Names[RTLIB::LOG_F80] = "logl";
Names[RTLIB::LOG_PPCF128] = "logl";
Names[RTLIB::LOG2_F32] = "log2f";
Names[RTLIB::LOG2_F64] = "log2";
Names[RTLIB::LOG2_F80] = "log2l";
Names[RTLIB::LOG2_PPCF128] = "log2l";
Names[RTLIB::LOG10_F32] = "log10f";
Names[RTLIB::LOG10_F64] = "log10";
Names[RTLIB::LOG10_F80] = "log10l";
Names[RTLIB::LOG10_PPCF128] = "log10l";
Names[RTLIB::EXP_F32] = "expf";
Names[RTLIB::EXP_F64] = "exp";
Names[RTLIB::EXP_F80] = "expl";
Names[RTLIB::EXP_PPCF128] = "expl";
Names[RTLIB::EXP2_F32] = "exp2f";
Names[RTLIB::EXP2_F64] = "exp2";
Names[RTLIB::EXP2_F80] = "exp2l";
Names[RTLIB::EXP2_PPCF128] = "exp2l";
Names[RTLIB::SIN_F32] = "sinf";
Names[RTLIB::SIN_F64] = "sin";
Names[RTLIB::SIN_F80] = "sinl";