mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-20 09:24:58 +00:00
Add intrinsics for log, log2, log10, exp, exp2.
No functional change (and no FE change to generate them). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55753 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
104e4ce162
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7794f2a3a7
@ -85,6 +85,26 @@ namespace RTLIB {
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SQRT_F64,
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SQRT_F80,
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SQRT_PPCF128,
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LOG_F32,
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LOG_F64,
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LOG_F80,
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LOG_PPCF128,
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LOG2_F32,
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LOG2_F64,
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LOG2_F80,
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LOG2_PPCF128,
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LOG10_F32,
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LOG10_F64,
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LOG10_F80,
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LOG10_PPCF128,
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EXP_F32,
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EXP_F64,
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EXP_F80,
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EXP_PPCF128,
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EXP2_F32,
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EXP2_F64,
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EXP2_F80,
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EXP2_PPCF128,
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SIN_F32,
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SIN_F64,
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SIN_F80,
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@ -426,9 +426,11 @@ namespace ISD {
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BIT_CONVERT,
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// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
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// FLOG, FLOG2, FLOG10, FEXP, FEXP2,
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// FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR - Perform various unary floating
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// point operations. These are inspired by libm.
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FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
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FLOG, FLOG2, FLOG10, FEXP, FEXP2,
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FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR,
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// LOAD and STORE have token chains as their first operand, then the same
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@ -200,6 +200,11 @@ let Properties = [IntrNoMem] in {
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def int_cos : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>]>;
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def int_pow : Intrinsic<[llvm_anyfloat_ty,
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LLVMMatchType<0>, LLVMMatchType<0>]>;
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def int_log : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>]>;
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def int_log10: Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>]>;
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def int_log2 : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>]>;
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def int_exp : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>]>;
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def int_exp2 : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>]>;
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}
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// NOTE: these are internal interfaces.
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@ -160,6 +160,81 @@ void IntrinsicLowering::AddPrototypes(Module &M) {
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I->arg_begin()->getType());
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}
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break;
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case Intrinsic::log:
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switch((int)I->arg_begin()->getType()->getTypeID()) {
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case Type::FloatTyID:
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EnsureFunctionExists(M, "logf", I->arg_begin(), I->arg_end(),
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Type::FloatTy);
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case Type::DoubleTyID:
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EnsureFunctionExists(M, "log", I->arg_begin(), I->arg_end(),
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Type::DoubleTy);
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case Type::X86_FP80TyID:
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case Type::FP128TyID:
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case Type::PPC_FP128TyID:
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EnsureFunctionExists(M, "logl", I->arg_begin(), I->arg_end(),
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I->arg_begin()->getType());
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}
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break;
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case Intrinsic::log2:
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switch((int)I->arg_begin()->getType()->getTypeID()) {
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case Type::FloatTyID:
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EnsureFunctionExists(M, "log2f", I->arg_begin(), I->arg_end(),
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Type::FloatTy);
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case Type::DoubleTyID:
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EnsureFunctionExists(M, "log2", I->arg_begin(), I->arg_end(),
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Type::DoubleTy);
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case Type::X86_FP80TyID:
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case Type::FP128TyID:
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case Type::PPC_FP128TyID:
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EnsureFunctionExists(M, "log2l", I->arg_begin(), I->arg_end(),
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I->arg_begin()->getType());
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}
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break;
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case Intrinsic::log10:
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switch((int)I->arg_begin()->getType()->getTypeID()) {
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case Type::FloatTyID:
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EnsureFunctionExists(M, "log10f", I->arg_begin(), I->arg_end(),
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Type::FloatTy);
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case Type::DoubleTyID:
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EnsureFunctionExists(M, "log10", I->arg_begin(), I->arg_end(),
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Type::DoubleTy);
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case Type::X86_FP80TyID:
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case Type::FP128TyID:
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case Type::PPC_FP128TyID:
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EnsureFunctionExists(M, "log10l", I->arg_begin(), I->arg_end(),
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I->arg_begin()->getType());
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}
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break;
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case Intrinsic::exp:
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switch((int)I->arg_begin()->getType()->getTypeID()) {
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case Type::FloatTyID:
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EnsureFunctionExists(M, "expf", I->arg_begin(), I->arg_end(),
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Type::FloatTy);
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case Type::DoubleTyID:
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EnsureFunctionExists(M, "exp", I->arg_begin(), I->arg_end(),
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Type::DoubleTy);
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case Type::X86_FP80TyID:
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case Type::FP128TyID:
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case Type::PPC_FP128TyID:
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EnsureFunctionExists(M, "expl", I->arg_begin(), I->arg_end(),
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I->arg_begin()->getType());
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}
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break;
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case Intrinsic::exp2:
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switch((int)I->arg_begin()->getType()->getTypeID()) {
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case Type::FloatTyID:
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EnsureFunctionExists(M, "exp2f", I->arg_begin(), I->arg_end(),
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Type::FloatTy);
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case Type::DoubleTyID:
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EnsureFunctionExists(M, "exp2", I->arg_begin(), I->arg_end(),
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Type::DoubleTy);
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case Type::X86_FP80TyID:
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case Type::FP128TyID:
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case Type::PPC_FP128TyID:
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EnsureFunctionExists(M, "exp2l", I->arg_begin(), I->arg_end(),
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I->arg_begin()->getType());
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}
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break;
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}
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}
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@ -857,6 +932,144 @@ void IntrinsicLowering::LowerIntrinsicCall(CallInst *CI) {
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}
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break;
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}
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case Intrinsic::log: {
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static Constant *logfFCache = 0;
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static Constant *logFCache = 0;
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static Constant *logLDCache = 0;
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switch (CI->getOperand(1)->getType()->getTypeID()) {
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default: assert(0 && "Invalid type in log"); abort();
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case Type::FloatTyID:
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ReplaceCallWith("logf", CI, CI->op_begin()+1, CI->op_end(),
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Type::FloatTy, logfFCache);
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break;
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case Type::DoubleTyID:
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ReplaceCallWith("log", CI, CI->op_begin()+1, CI->op_end(),
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Type::DoubleTy, logFCache);
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break;
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case Type::X86_FP80TyID:
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case Type::FP128TyID:
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case Type::PPC_FP128TyID:
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ReplaceCallWith("logl", CI, CI->op_begin()+1, CI->op_end(),
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CI->getOperand(1)->getType(), logLDCache);
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break;
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}
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break;
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}
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case Intrinsic::log2: {
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static Constant *log2fFCache = 0;
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static Constant *log2FCache = 0;
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static Constant *log2LDCache = 0;
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switch (CI->getOperand(1)->getType()->getTypeID()) {
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default: assert(0 && "Invalid type in log2"); abort();
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case Type::FloatTyID:
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ReplaceCallWith("log2f", CI, CI->op_begin()+1, CI->op_end(),
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Type::FloatTy, log2fFCache);
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break;
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case Type::DoubleTyID:
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ReplaceCallWith("log2", CI, CI->op_begin()+1, CI->op_end(),
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Type::DoubleTy, log2FCache);
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break;
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case Type::X86_FP80TyID:
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case Type::FP128TyID:
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case Type::PPC_FP128TyID:
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ReplaceCallWith("log2l", CI, CI->op_begin()+1, CI->op_end(),
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CI->getOperand(1)->getType(), log2LDCache);
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break;
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}
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break;
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}
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case Intrinsic::log10: {
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static Constant *log10fFCache = 0;
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static Constant *log10FCache = 0;
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static Constant *log10LDCache = 0;
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switch (CI->getOperand(1)->getType()->getTypeID()) {
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default: assert(0 && "Invalid type in log10"); abort();
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case Type::FloatTyID:
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ReplaceCallWith("log10f", CI, CI->op_begin()+1, CI->op_end(),
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Type::FloatTy, log10fFCache);
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break;
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case Type::DoubleTyID:
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ReplaceCallWith("log10", CI, CI->op_begin()+1, CI->op_end(),
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Type::DoubleTy, log10FCache);
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break;
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case Type::X86_FP80TyID:
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case Type::FP128TyID:
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case Type::PPC_FP128TyID:
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ReplaceCallWith("log10l", CI, CI->op_begin()+1, CI->op_end(),
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CI->getOperand(1)->getType(), log10LDCache);
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break;
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}
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break;
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}
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case Intrinsic::exp: {
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static Constant *expfFCache = 0;
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static Constant *expFCache = 0;
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static Constant *expLDCache = 0;
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switch (CI->getOperand(1)->getType()->getTypeID()) {
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default: assert(0 && "Invalid type in exp"); abort();
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case Type::FloatTyID:
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ReplaceCallWith("expf", CI, CI->op_begin()+1, CI->op_end(),
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Type::FloatTy, expfFCache);
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break;
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case Type::DoubleTyID:
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ReplaceCallWith("exp", CI, CI->op_begin()+1, CI->op_end(),
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Type::DoubleTy, expFCache);
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break;
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case Type::X86_FP80TyID:
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case Type::FP128TyID:
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case Type::PPC_FP128TyID:
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ReplaceCallWith("expl", CI, CI->op_begin()+1, CI->op_end(),
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CI->getOperand(1)->getType(), expLDCache);
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break;
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}
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break;
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}
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case Intrinsic::exp2: {
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static Constant *exp2fFCache = 0;
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static Constant *exp2FCache = 0;
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static Constant *exp2LDCache = 0;
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switch (CI->getOperand(1)->getType()->getTypeID()) {
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default: assert(0 && "Invalid type in exp2"); abort();
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case Type::FloatTyID:
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ReplaceCallWith("exp2f", CI, CI->op_begin()+1, CI->op_end(),
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Type::FloatTy, exp2fFCache);
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break;
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case Type::DoubleTyID:
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ReplaceCallWith("exp2", CI, CI->op_begin()+1, CI->op_end(),
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Type::DoubleTy, exp2FCache);
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break;
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case Type::X86_FP80TyID:
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case Type::FP128TyID:
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case Type::PPC_FP128TyID:
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ReplaceCallWith("exp2l", CI, CI->op_begin()+1, CI->op_end(),
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CI->getOperand(1)->getType(), exp2LDCache);
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break;
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}
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break;
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}
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case Intrinsic::pow: {
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static Constant *powfFCache = 0;
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static Constant *powFCache = 0;
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static Constant *powLDCache = 0;
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switch (CI->getOperand(1)->getType()->getTypeID()) {
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default: assert(0 && "Invalid type in pow"); abort();
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case Type::FloatTyID:
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ReplaceCallWith("powf", CI, CI->op_begin()+1, CI->op_end(),
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Type::FloatTy, powfFCache);
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break;
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case Type::DoubleTyID:
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ReplaceCallWith("pow", CI, CI->op_begin()+1, CI->op_end(),
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Type::DoubleTy, powFCache);
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break;
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case Type::X86_FP80TyID:
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case Type::FP128TyID:
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case Type::PPC_FP128TyID:
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ReplaceCallWith("powl", CI, CI->op_begin()+1, CI->op_end(),
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CI->getOperand(1)->getType(), powLDCache);
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break;
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}
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break;
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}
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case Intrinsic::flt_rounds:
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// Lower to "round to the nearest"
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if (CI->getType() != Type::VoidTy)
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@ -3490,6 +3490,11 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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case ISD::FSQRT:
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case ISD::FSIN:
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case ISD::FCOS:
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case ISD::FLOG:
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case ISD::FLOG2:
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case ISD::FLOG10:
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case ISD::FEXP:
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case ISD::FEXP2:
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case ISD::FTRUNC:
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case ISD::FFLOOR:
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case ISD::FCEIL:
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@ -3526,6 +3531,11 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
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break;
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}
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case ISD::FLOG:
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case ISD::FLOG2:
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case ISD::FLOG10:
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case ISD::FEXP:
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case ISD::FEXP2:
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case ISD::FTRUNC:
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case ISD::FFLOOR:
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case ISD::FCEIL:
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@ -3556,6 +3566,26 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
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RTLIB::COS_F80, RTLIB::COS_PPCF128);
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break;
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case ISD::FLOG:
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LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
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RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
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break;
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case ISD::FLOG2:
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LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
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RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
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break;
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case ISD::FLOG10:
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LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
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RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
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break;
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case ISD::FEXP:
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LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
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RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
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break;
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case ISD::FEXP2:
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LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
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RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
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break;
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case ISD::FTRUNC:
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LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
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RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
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@ -4163,6 +4193,11 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
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// precision, and these operations don't modify precision at all.
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break;
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case ISD::FLOG:
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case ISD::FLOG2:
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case ISD::FLOG10:
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case ISD::FEXP:
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case ISD::FEXP2:
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case ISD::FSQRT:
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case ISD::FSIN:
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case ISD::FCOS:
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@ -6574,6 +6609,11 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
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RTLIB::POWI_PPCF128),
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Node, false, Hi);
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break;
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case ISD::FLOG:
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case ISD::FLOG2:
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case ISD::FLOG10:
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case ISD::FEXP:
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case ISD::FEXP2:
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case ISD::FTRUNC:
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case ISD::FFLOOR:
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case ISD::FCEIL:
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@ -6596,6 +6636,26 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
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LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
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RTLIB::COS_F80, RTLIB::COS_PPCF128);
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break;
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case ISD::FLOG:
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LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
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RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
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break;
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case ISD::FLOG2:
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LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
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RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
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break;
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case ISD::FLOG10:
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LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
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RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
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break;
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case ISD::FEXP:
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LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
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RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
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break;
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case ISD::FEXP2:
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LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
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RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
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break;
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case ISD::FTRUNC:
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LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
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RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
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@ -6966,6 +7026,11 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
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case ISD::FSQRT:
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case ISD::FSIN:
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case ISD::FCOS:
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case ISD::FLOG:
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case ISD::FLOG2:
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case ISD::FLOG10:
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case ISD::FEXP:
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case ISD::FEXP2:
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case ISD::FP_TO_SINT:
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case ISD::FP_TO_UINT:
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case ISD::SINT_TO_FP:
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@ -7102,6 +7167,11 @@ SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
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case ISD::FSQRT:
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case ISD::FSIN:
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case ISD::FCOS:
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case ISD::FLOG:
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case ISD::FLOG2:
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case ISD::FLOG10:
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case ISD::FEXP:
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case ISD::FEXP2:
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case ISD::FP_TO_SINT:
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case ISD::FP_TO_UINT:
|
||||
case ISD::SINT_TO_FP:
|
||||
|
@ -3015,6 +3015,31 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
|
||||
getValue(I.getOperand(1)).getValueType(),
|
||||
getValue(I.getOperand(1))));
|
||||
return 0;
|
||||
case Intrinsic::log:
|
||||
setValue(&I, DAG.getNode(ISD::FLOG,
|
||||
getValue(I.getOperand(1)).getValueType(),
|
||||
getValue(I.getOperand(1))));
|
||||
return 0;
|
||||
case Intrinsic::log2:
|
||||
setValue(&I, DAG.getNode(ISD::FLOG2,
|
||||
getValue(I.getOperand(1)).getValueType(),
|
||||
getValue(I.getOperand(1))));
|
||||
return 0;
|
||||
case Intrinsic::log10:
|
||||
setValue(&I, DAG.getNode(ISD::FLOG10,
|
||||
getValue(I.getOperand(1)).getValueType(),
|
||||
getValue(I.getOperand(1))));
|
||||
return 0;
|
||||
case Intrinsic::exp:
|
||||
setValue(&I, DAG.getNode(ISD::FEXP,
|
||||
getValue(I.getOperand(1)).getValueType(),
|
||||
getValue(I.getOperand(1))));
|
||||
return 0;
|
||||
case Intrinsic::exp2:
|
||||
setValue(&I, DAG.getNode(ISD::FEXP2,
|
||||
getValue(I.getOperand(1)).getValueType(),
|
||||
getValue(I.getOperand(1))));
|
||||
return 0;
|
||||
case Intrinsic::pow:
|
||||
setValue(&I, DAG.getNode(ISD::FPOW,
|
||||
getValue(I.getOperand(1)).getValueType(),
|
||||
|
@ -83,6 +83,26 @@ static void InitLibcallNames(const char **Names) {
|
||||
Names[RTLIB::SQRT_F64] = "sqrt";
|
||||
Names[RTLIB::SQRT_F80] = "sqrtl";
|
||||
Names[RTLIB::SQRT_PPCF128] = "sqrtl";
|
||||
Names[RTLIB::LOG_F32] = "logf";
|
||||
Names[RTLIB::LOG_F64] = "log";
|
||||
Names[RTLIB::LOG_F80] = "logl";
|
||||
Names[RTLIB::LOG_PPCF128] = "logl";
|
||||
Names[RTLIB::LOG2_F32] = "log2f";
|
||||
Names[RTLIB::LOG2_F64] = "log2";
|
||||
Names[RTLIB::LOG2_F80] = "log2l";
|
||||
Names[RTLIB::LOG2_PPCF128] = "log2l";
|
||||
Names[RTLIB::LOG10_F32] = "log10f";
|
||||
Names[RTLIB::LOG10_F64] = "log10";
|
||||
Names[RTLIB::LOG10_F80] = "log10l";
|
||||
Names[RTLIB::LOG10_PPCF128] = "log10l";
|
||||
Names[RTLIB::EXP_F32] = "expf";
|
||||
Names[RTLIB::EXP_F64] = "exp";
|
||||
Names[RTLIB::EXP_F80] = "expl";
|
||||
Names[RTLIB::EXP_PPCF128] = "expl";
|
||||
Names[RTLIB::EXP2_F32] = "exp2f";
|
||||
Names[RTLIB::EXP2_F64] = "exp2";
|
||||
Names[RTLIB::EXP2_F80] = "exp2l";
|
||||
Names[RTLIB::EXP2_PPCF128] = "exp2l";
|
||||
Names[RTLIB::SIN_F32] = "sinf";
|
||||
Names[RTLIB::SIN_F64] = "sin";
|
||||
Names[RTLIB::SIN_F80] = "sinl";
|
||||
|
@ -243,6 +243,16 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
|
||||
setOperationAction(ISD::FCOS , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FREM , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FREM , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FLOG , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FLOG , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FLOG2 , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FLOG2 , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FLOG10 , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FLOG10 , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FEXP , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FEXP , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FEXP2 , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FEXP2 , MVT::f32, Expand);
|
||||
if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
|
||||
setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
|
||||
setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
|
||||
|
@ -99,6 +99,17 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
|
||||
setOperationAction(ISD::FPOW , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FPOW , MVT::f64, Expand);
|
||||
|
||||
setOperationAction(ISD::FLOG, MVT::f32, Expand);
|
||||
setOperationAction(ISD::FLOG, MVT::f64, Expand);
|
||||
setOperationAction(ISD::FLOG2, MVT::f32, Expand);
|
||||
setOperationAction(ISD::FLOG2, MVT::f64, Expand);
|
||||
setOperationAction(ISD::FLOG10, MVT::f32, Expand);
|
||||
setOperationAction(ISD::FLOG10, MVT::f64, Expand);
|
||||
setOperationAction(ISD::FEXP, MVT::f32, Expand);
|
||||
setOperationAction(ISD::FEXP, MVT::f64, Expand);
|
||||
setOperationAction(ISD::FEXP2, MVT::f32, Expand);
|
||||
setOperationAction(ISD::FEXP2, MVT::f64, Expand);
|
||||
|
||||
setOperationAction(ISD::SETCC, MVT::f32, Promote);
|
||||
|
||||
setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote);
|
||||
|
@ -189,9 +189,19 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
|
||||
setOperationAction(ISD::FSIN , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FCOS , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FREM , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FLOG , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FLOG2, MVT::f64, Expand);
|
||||
setOperationAction(ISD::FLOG10,MVT::f64, Expand);
|
||||
setOperationAction(ISD::FEXP , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FEXP2, MVT::f64, Expand);
|
||||
setOperationAction(ISD::FSIN , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FCOS , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FREM , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FLOG , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FLOG2, MVT::f32, Expand);
|
||||
setOperationAction(ISD::FLOG10,MVT::f32, Expand);
|
||||
setOperationAction(ISD::FEXP , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FEXP2, MVT::f32, Expand);
|
||||
|
||||
// If we're enabling GP optimizations, use hardware square root
|
||||
setOperationAction(ISD::FSQRT, MVT::f64, Expand);
|
||||
|
@ -75,10 +75,20 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
|
||||
setOperationAction(ISD::FCOS , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FSQRT, MVT::f64, Expand);
|
||||
setOperationAction(ISD::FPOW , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FLOG , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FLOG2, MVT::f64, Expand);
|
||||
setOperationAction(ISD::FLOG10,MVT::f64, Expand);
|
||||
setOperationAction(ISD::FEXP , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FEXP2, MVT::f64, Expand);
|
||||
setOperationAction(ISD::FSIN , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FCOS , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FSQRT, MVT::f32, Expand);
|
||||
setOperationAction(ISD::FPOW , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FLOG , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FLOG2, MVT::f32, Expand);
|
||||
setOperationAction(ISD::FLOG10,MVT::f32, Expand);
|
||||
setOperationAction(ISD::FEXP , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FEXP2, MVT::f32, Expand);
|
||||
|
||||
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
|
||||
|
||||
|
@ -99,10 +99,20 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
|
||||
setOperationAction(ISD::FCOS , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FREM , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FPOW , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FLOG , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FLOG2, MVT::f64, Expand);
|
||||
setOperationAction(ISD::FLOG10,MVT::f64, Expand);
|
||||
setOperationAction(ISD::FEXP ,MVT::f64, Expand);
|
||||
setOperationAction(ISD::FEXP2 ,MVT::f64, Expand);
|
||||
setOperationAction(ISD::FSIN , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FCOS , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FREM , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FPOW , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FLOG , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FLOG2 ,MVT::f32, Expand);
|
||||
setOperationAction(ISD::FLOG10,MVT::f32, Expand);
|
||||
setOperationAction(ISD::FEXP ,MVT::f32, Expand);
|
||||
setOperationAction(ISD::FEXP2 ,MVT::f32, Expand);
|
||||
|
||||
setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
|
||||
|
||||
@ -350,6 +360,11 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
|
||||
setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
|
||||
setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
|
||||
setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
|
||||
setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
|
||||
setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
|
||||
setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
|
||||
setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
|
||||
setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
|
||||
}
|
||||
|
||||
computeRegisterProperties();
|
||||
|
@ -586,6 +586,16 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
|
||||
setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
|
||||
setOperationAction(ISD::FPOW , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FPOW , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FLOG , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FLOG , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FLOG2, MVT::f64, Expand);
|
||||
setOperationAction(ISD::FLOG2, MVT::f32, Expand);
|
||||
setOperationAction(ISD::FLOG10, MVT::f64, Expand);
|
||||
setOperationAction(ISD::FLOG10, MVT::f32, Expand);
|
||||
setOperationAction(ISD::FEXP , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FEXP , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FEXP2, MVT::f64, Expand);
|
||||
setOperationAction(ISD::FEXP2, MVT::f32, Expand);
|
||||
|
||||
setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
|
||||
setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
|
||||
|
@ -494,6 +494,22 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
|
||||
setOperationAction(ISD::FPOW , MVT::f64 , Expand);
|
||||
setOperationAction(ISD::FPOW , MVT::f80 , Expand);
|
||||
|
||||
setOperationAction(ISD::FLOG, MVT::f32, Expand);
|
||||
setOperationAction(ISD::FLOG, MVT::f64, Expand);
|
||||
setOperationAction(ISD::FLOG, MVT::f80, Expand);
|
||||
setOperationAction(ISD::FLOG2, MVT::f32, Expand);
|
||||
setOperationAction(ISD::FLOG2, MVT::f64, Expand);
|
||||
setOperationAction(ISD::FLOG2, MVT::f80, Expand);
|
||||
setOperationAction(ISD::FLOG10, MVT::f32, Expand);
|
||||
setOperationAction(ISD::FLOG10, MVT::f64, Expand);
|
||||
setOperationAction(ISD::FLOG10, MVT::f80, Expand);
|
||||
setOperationAction(ISD::FEXP, MVT::f32, Expand);
|
||||
setOperationAction(ISD::FEXP, MVT::f64, Expand);
|
||||
setOperationAction(ISD::FEXP, MVT::f80, Expand);
|
||||
setOperationAction(ISD::FEXP2, MVT::f32, Expand);
|
||||
setOperationAction(ISD::FEXP2, MVT::f64, Expand);
|
||||
setOperationAction(ISD::FEXP2, MVT::f80, Expand);
|
||||
|
||||
// First set operation action for all vector types to expand. Then we
|
||||
// will selectively turn on ones that can be effectively codegen'd.
|
||||
for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
|
||||
|
Loading…
Reference in New Issue
Block a user