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Fix a copy-and-paste duplication error in the PPC 440 and A2 schedules (no functionality change).

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157912 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2012-06-04 02:39:52 +00:00
parent 77838f9ca9
commit 77a9e0f318
2 changed files with 0 additions and 42 deletions
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20
lib/Target/PowerPC/PPCSchedule440.td
View File

@ -373,26 +373,6 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [LWB]>],
[8, 5],
[NoBypass, GPR_Bypass]>,
InstrItinData<LdStSTD , [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [LRACC]>,
InstrStage<1, [AGEN]>,
InstrStage<1, [CRD]>,
InstrStage<2, [LWB]>],
[8, 5],
[NoBypass, GPR_Bypass]>,
InstrItinData<LdStSTDCX , [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1]>,
InstrStage<1, [IRACC], 0>,
InstrStage<4, [LWARX_Hold], 0>,
InstrStage<1, [LRACC]>,
InstrStage<1, [AGEN]>,
InstrStage<1, [CRD]>,
InstrStage<1, [LWB]>],
[8, 5],
[NoBypass, GPR_Bypass]>,
InstrItinData<LdStSTWCX , [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1]>,

22
lib/Target/PowerPC/PPCScheduleA2.td
View File

@ -379,28 +379,6 @@ def PPCA2Itineraries : ProcessorItineraries<
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
[26, 7],
[NoBypass, GPR_Bypass]>,
InstrItinData<LdStSTD , [InstrStage<4,
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
IU4_4, IU4_5, IU4_6, IU4_7]>,
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
[13, 7],
[GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStSTDCX , [InstrStage<4,
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
IU4_4, IU4_5, IU4_6, IU4_7]>,
InstrStage<1, [IU5]>, InstrStage<13, [IU6]>,
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
[26, 7],
[NoBypass, GPR_Bypass]>,
InstrItinData<LdStSTWCX , [InstrStage<4,
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,