move fconst[sd] to UAL. <rdar://7414913>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89700 91177308-0d34-0410-b5e6-96231b3b80d8

test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll

@@ -13,7 +13,7 @@ entry:
   %4 = fadd float 0.000000e+00, %3                ; <float> [#uses=1]
   %5 = fsub float 1.000000e+00, %4                ; <float> [#uses=1]
 ; CHECK: foo:
-; CHECK: fconsts s{{[0-9]+}}, #112
+; CHECK: vmov.f32 s{{[0-9]+}}, #1.000000e+00
   %6 = fsub float 1.000000e+00, undef             ; <float> [#uses=2]
   %7 = fsub float %2, undef                       ; <float> [#uses=1]
   %8 = fsub float 0.000000e+00, undef             ; <float> [#uses=3]

test/CodeGen/ARM/fpconsts.ll

@@ -3,7 +3,7 @@
 define arm_apcscc float @t1(float %x) nounwind readnone optsize {
 entry:
 ; CHECK: t1:
-; CHECK: fconsts s1, #16
+; CHECK: vmov.f32 s1, #4.000000e+00
   %0 = fadd float %x, 4.000000e+00
   ret float %0
 }
@@ -11,7 +11,7 @@ entry:
 define arm_apcscc double @t2(double %x) nounwind readnone optsize {
 entry:
 ; CHECK: t2:
-; CHECK: fconstd d1, #8
+; CHECK: vmov.f64 d1, #3.000000e+00
   %0 = fadd double %x, 3.000000e+00
   ret double %0
 }
@@ -19,7 +19,7 @@ entry:
 define arm_apcscc double @t3(double %x) nounwind readnone optsize {
 entry:
 ; CHECK: t3:
-; CHECK: fconstd d1, #170
+; CHECK: vmov.f64 d1, #-1.300000e+01
   %0 = fmul double %x, -1.300000e+01
   ret double %0
 }
@@ -27,7 +27,7 @@ entry:
 define arm_apcscc float @t4(float %x) nounwind readnone optsize {
 entry:
 ; CHECK: t4:
-; CHECK: fconsts s1, #184
+; CHECK: vmov.f32 s1, #-2.400000e+01
   %0 = fmul float %x, -2.400000e+01
   ret float %0
 }

test/CodeGen/Thumb2/cross-rc-coalescing-2.ll

@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep vmov.f32 | count 6
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep vmov.f32 | count 7
 
 define arm_apcscc void @fht(float* nocapture %fz, i16 signext %n) nounwind {
 entry: