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[Hexagon] Removing old versions of cmph and updating references.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226013 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2015-01-14 18:26:14 +00:00
parent ad946a868f
commit 77b1c04ef8
3 changed files with 11 additions and 107 deletions
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2
lib/Target/Hexagon/HexagonHardwareLoops.cpp
View File

@ -554,7 +554,7 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L,
break;
// Very limited support for byte/halfword compares.
case Hexagon::A4_cmpbeqi:
case Hexagon::CMPhEQri_V4: {
case Hexagon::A4_cmpheqi: {
if (IVBump != 1)
return nullptr;

22
lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -366,12 +366,11 @@ bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
SrcReg = MI->getOperand(1).getReg();
Mask = 0xFF;
break;
case Hexagon::CMPhEQri_V4:
case Hexagon::CMPhEQrr_shl_V4:
case Hexagon::CMPhEQrr_xor_V4:
case Hexagon::CMPhGTUri_V4:
case Hexagon::CMPhGTUrr_V4:
case Hexagon::CMPhGTrr_shl_V4:
case Hexagon::A4_cmpheqi:
case Hexagon::A4_cmpheq:
case Hexagon::A4_cmphgtui:
case Hexagon::A4_cmphgtu:
case Hexagon::A4_cmphgt:
SrcReg = MI->getOperand(1).getReg();
Mask = 0xFFFF;
break;
@ -388,10 +387,9 @@ bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
case Hexagon::A4_cmpbeq:
case Hexagon::A4_cmpbgtu:
case Hexagon::A4_cmpbgt:
case Hexagon::CMPhEQrr_shl_V4:
case Hexagon::CMPhEQrr_xor_V4:
case Hexagon::CMPhGTUrr_V4:
case Hexagon::CMPhGTrr_shl_V4:
case Hexagon::A4_cmpheq:
case Hexagon::A4_cmphgtu:
case Hexagon::A4_cmphgt:
SrcReg2 = MI->getOperand(2).getReg();
return true;
@ -400,8 +398,8 @@ bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
case Hexagon::C2_cmpgti:
case Hexagon::A4_cmpbeqi:
case Hexagon::A4_cmpbgtui:
case Hexagon::CMPhEQri_V4:
case Hexagon::CMPhGTUri_V4:
case Hexagon::A4_cmpheqi:
case Hexagon::A4_cmphgtui:
SrcReg2 = 0;
Value = MI->getOperand(2).getImm();
return true;

94
lib/Target/Hexagon/HexagonInstrInfoV4.td
View File

@ -2924,100 +2924,6 @@ def : Pat <(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
0, 1))>,
Requires<[HasV4T]>;
// Following instruction is not being extended as it results into the incorrect
// code for negative numbers.
// Signed half compare(.eq) ri.
// Pd=cmph.eq(Rs,#s8)
let isCompare = 1, validSubTargets = HasV4SubT in
def CMPhEQri_V4 : MInst<(outs PredRegs:$dst),
(ins IntRegs:$src1, s8Imm:$src2),
"$dst = cmph.eq($src1, #$src2)",
[(set (i1 PredRegs:$dst), (seteq (and (i32 IntRegs:$src1), 65535),
s8ImmPred:$src2))]>,
Requires<[HasV4T]>;
// Signed half compare(.eq) rr.
// Case 1: xor + and, then compare:
// r0=xor(r0,r1)
// r0=and(r0,#0xffff)
// p0=cmp.eq(r0,#0)
// Pd=cmph.eq(Rs,Rt)
let isCompare = 1, validSubTargets = HasV4SubT in
def CMPhEQrr_xor_V4 : MInst<(outs PredRegs:$dst),
(ins IntRegs:$src1, IntRegs:$src2),
"$dst = cmph.eq($src1, $src2)",
[(set (i1 PredRegs:$dst), (seteq (and (xor (i32 IntRegs:$src1),
(i32 IntRegs:$src2)),
65535), 0))]>,
Requires<[HasV4T]>;
// Signed half compare(.eq) rr.
// Case 2: shift left 16 bits then compare:
// r0=asl(r0,16)
// r1=asl(r1,16)
// p0=cmp.eq(r0,r1)
// Pd=cmph.eq(Rs,Rt)
let isCompare = 1, validSubTargets = HasV4SubT in
def CMPhEQrr_shl_V4 : MInst<(outs PredRegs:$dst),
(ins IntRegs:$src1, IntRegs:$src2),
"$dst = cmph.eq($src1, $src2)",
[(set (i1 PredRegs:$dst),
(seteq (shl (i32 IntRegs:$src1), (i32 16)),
(shl (i32 IntRegs:$src2), (i32 16))))]>,
Requires<[HasV4T]>;
/* Incorrect Pattern -- immediate should be right shifted before being
used in the cmph.gt instruction.
// Signed half compare(.gt) ri.
// Pd=cmph.gt(Rs,#s8)
let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
isCompare = 1, validSubTargets = HasV4SubT in
def CMPhGTri_V4 : MInst<(outs PredRegs:$dst),
(ins IntRegs:$src1, s8Ext:$src2),
"$dst = cmph.gt($src1, #$src2)",
[(set (i1 PredRegs:$dst),
(setgt (shl (i32 IntRegs:$src1), (i32 16)),
s8ExtPred:$src2))]>,
Requires<[HasV4T]>;
*/
// Signed half compare(.gt) rr.
// Pd=cmph.gt(Rs,Rt)
let isCompare = 1, validSubTargets = HasV4SubT in
def CMPhGTrr_shl_V4 : MInst<(outs PredRegs:$dst),
(ins IntRegs:$src1, IntRegs:$src2),
"$dst = cmph.gt($src1, $src2)",
[(set (i1 PredRegs:$dst),
(setgt (shl (i32 IntRegs:$src1), (i32 16)),
(shl (i32 IntRegs:$src2), (i32 16))))]>,
Requires<[HasV4T]>;
// Unsigned half compare rr (.gtu).
// Pd=cmph.gtu(Rs,Rt)
let isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPhGTU",
InputType = "reg" in
def CMPhGTUrr_V4 : MInst<(outs PredRegs:$dst),
(ins IntRegs:$src1, IntRegs:$src2),
"$dst = cmph.gtu($src1, $src2)",
[(set (i1 PredRegs:$dst),
(setugt (and (i32 IntRegs:$src1), 65535),
(and (i32 IntRegs:$src2), 65535)))]>,
Requires<[HasV4T]>, ImmRegRel;
// Unsigned half compare ri (.gtu).
// Pd=cmph.gtu(Rs,#u7)
let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 7,
isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPhGTU",
InputType = "imm" in
def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst),
(ins IntRegs:$src1, u7Ext:$src2),
"$dst = cmph.gtu($src1, #$src2)",
[(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 65535),
u7ExtPred:$src2))]>,
Requires<[HasV4T]>, ImmRegRel;
let validSubTargets = HasV4SubT in
def NTSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
"$dst = !tstbit($src1, $src2)",