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AArch64: Simplify logic in deciding whether bfi is valid

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Previous code had a confusing comment which was mostly an implementation
detail. This condition corresponds to "lsb up to register width" and "width not
ridiculous".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174877 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2013-02-11 12:32:18 +00:00
parent b05dc55460
commit 77b1c9cf57
1 changed files with 1 additions and 6 deletions
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7
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
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@ -1725,12 +1725,7 @@ validateInstruction(MCInst &Inst,
int64_t ImmR = Inst.getOperand(ImmOps).getImm();
int64_t ImmS = Inst.getOperand(ImmOps+1).getImm();
if (ImmR == 0) {
// Bitfield inserts are preferred disassembly if ImmS < ImmR. However,
// there is this one case where insert is valid syntax but the bfx
// disassembly should be used: e.g. "sbfiz w0, w0, #0, #1".
return false;
} else if (ImmS >= ImmR) {
if (ImmR != 0 && ImmS >= ImmR) {
return Error(Operands[4]->getStartLoc(),
"requested insert overflows register");
}