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Add saving and restoring of r30 to the prologue and epilogue, respectively

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Summary: The PIC additions didn't update the prologue and epilogue code to save and restore r30 (PIC base register).  This does that.

Test Plan: Tests updated.

Reviewers: hfinkel

Reviewed By: hfinkel

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6876

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225450 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Justin Hibbits 2015-01-08 15:47:19 +00:00
parent f5aa68179c
commit 77e85a150c
4 changed files with 23 additions and 2 deletions
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16
lib/Target/PowerPC/PPCFrameLowering.cpp
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@ -644,6 +644,14 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
.addImm(FPOffset)
.addReg(SPReg);
if (isPIC && !isDarwinABI && !isPPC64 &&
MF.getInfo<PPCFunctionInfo>()->usesPICBase())
// FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
BuildMI(MBB, MBBI, dl, StoreInst)
.addReg(PPC::R30)
.addImm(-8U)
.addReg(SPReg);
if (HasBP)
// FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
BuildMI(MBB, MBBI, dl, StoreInst)
@ -1003,6 +1011,14 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
.addImm(FPOffset)
.addReg(SPReg);
if (isPIC && !isDarwinABI && !isPPC64 &&
MF.getInfo<PPCFunctionInfo>()->usesPICBase())
// FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
BuildMI(MBB, MBBI, dl, LoadInst)
.addReg(PPC::R30)
.addImm(-8U)
.addReg(SPReg);
if (HasBP)
BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
.addImm(BPOffset)

1
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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@ -307,6 +307,7 @@ SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
if (M->getPICLevel() == PICLevel::Small) {
BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MoveGOTtoLR));
BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
} else {
BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);

4
test/CodeGen/PowerPC/ppc32-pic-large.ll
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@ -12,12 +12,14 @@ entry:
; LARGE-BSS: [[POFF:\.L[0-9]+\$poff]]:
; LARGE-BSS-NEXT: .long .LTOC-[[PB:\.L[0-9]+\$pb]]
; LARGE-BSS-NEXT: foo:
; LARGE-BSS: stw 30, -8(1)
; LARGE-BSS: bl [[PB]]
; LARGE-BSS-NEXT: [[PB]]:
; LARGE-BSS: mflr 30
; LARGE-BSS: lwz [[REG:[0-9]+]], [[POFF]]-[[PB]](30)
; LARGE-BSS-NEXT: add 30, [[REG]], 30
; LARGE-BSS: lwz [[VREG:[0-9]+]], [[VREF:\.LC[0-9]+]]-.LTOC(30)
; LARGE-BSS: lwz {{[0-9]+}}, 0([[VREG]])
; LARGE-BSS-DAG: lwz {{[0-9]+}}, 0([[VREG]])
; LARGE-BSS-DAG: lwz 30, -8(1)
; LARGE-BSS: [[VREF]]:
; LARGE-BSS-NEXT: .long bar

4
test/CodeGen/PowerPC/ppc32-pic.ll
View File

@ -10,7 +10,9 @@ entry:
!llvm.module.flags = !{!0}
!0 = !{i32 1, !"PIC Level", i32 1}
; SMALL-BSS-LABEL:foo:
; SMALL-BSS: stw 30, -8(1)
; SMALL-BSS: bl _GLOBAL_OFFSET_TABLE_@local-4
; SMALL-BSS: mflr 30
; SMALL-BSS: lwz [[VREG:[0-9]+]], bar@GOT(30)
; SMALL-BSS: lwz {{[0-9]+}}, 0([[VREG]])
; SMALL-BSS-DAG: lwz {{[0-9]+}}, 0([[VREG]])
; SMALL-BSS-DAG: lwz 30, -8(1)