From 77f7a5771e01ec5ec5fdbb3af8fcc2ce31e1d4f7 Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Wed, 28 Jan 2009 02:58:31 +0000 Subject: [PATCH] Use ZERO_EXTEND instead of ANY_EXTEND when promoting shift amounts, to avoid implicitly assuming that target architectures will ignore the high bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63169 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 2 +- lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 58ac8c285c9..4ee17bf807c 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -974,7 +974,7 @@ SDValue SelectionDAGLegalize::LegalizeShiftAmount(SDValue ShiftAmt) { return DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), ShiftAmt); if (TLI.getShiftAmountTy().bitsGT(ShiftAmt.getValueType())) - return DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), ShiftAmt); + return DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), ShiftAmt); return ShiftAmt; } diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 3823f65263a..420a8d374c6 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -114,7 +114,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_ShiftOp(SDNode *N) { if (TLI.getShiftAmountTy().bitsLT(ShiftAmt.getValueType())) ShiftAmt = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), ShiftAmt); else if (TLI.getShiftAmountTy().bitsGT(ShiftAmt.getValueType())) - ShiftAmt = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), ShiftAmt); + ShiftAmt = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), ShiftAmt); return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, ShiftAmt); }