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Rename ConstantSDNode's getSignExtended to getSExtValue, for

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consistancy with ConstantInt, and re-implement it in terms
of ConstantInt's getSExtValue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56700 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-09-26 21:54:37 +00:00
parent f275250333
commit 7810bfed55
10 changed files with 30 additions and 34 deletions
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6
include/llvm/CodeGen/SelectionDAGNodes.h
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@ -1721,11 +1721,7 @@ public:
const ConstantInt *getConstantIntValue() const { return Value; } const ConstantInt *getConstantIntValue() const { return Value; }
const APInt &getAPIntValue() const { return Value->getValue(); } const APInt &getAPIntValue() const { return Value->getValue(); }
uint64_t getZExtValue() const { return Value->getZExtValue(); } uint64_t getZExtValue() const { return Value->getZExtValue(); }
int64_t getSExtValue() const { return Value->getSExtValue(); }
int64_t getSignExtended() const {
unsigned Bits = getValueType(0).getSizeInBits();
return ((int64_t)getZExtValue() << (64-Bits)) >> (64-Bits);
}
bool isNullValue() const { return Value->isNullValue(); } bool isNullValue() const { return Value->isNullValue(); }
bool isAllOnesValue() const { return Value->isAllOnesValue(); } bool isAllOnesValue() const { return Value->isAllOnesValue(); }

14
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -1170,12 +1170,12 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
DAG.getConstant(N1C->getAPIntValue().logBase2(), DAG.getConstant(N1C->getAPIntValue().logBase2(),
TLI.getShiftAmountTy())); TLI.getShiftAmountTy()));
// fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { if (N1C && isPowerOf2_64(-N1C->getSExtValue())) {
// FIXME: If the input is something that is easily negated (e.g. a // FIXME: If the input is something that is easily negated (e.g. a
// single-use add), we should put the negate there. // single-use add), we should put the negate there.
return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
DAG.getNode(ISD::SHL, VT, N0, DAG.getNode(ISD::SHL, VT, N0,
DAG.getConstant(Log2_64(-N1C->getSignExtended()), DAG.getConstant(Log2_64(-N1C->getSExtValue()),
TLI.getShiftAmountTy()))); TLI.getShiftAmountTy())));
} }
@ -1238,7 +1238,7 @@ SDValue DAGCombiner::visitSDIV(SDNode *N) {
if (N0C && N1C && !N1C->isNullValue()) if (N0C && N1C && !N1C->isNullValue())
return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
// fold (sdiv X, 1) -> X // fold (sdiv X, 1) -> X
if (N1C && N1C->getSignExtended() == 1LL) if (N1C && N1C->getSExtValue() == 1LL)
return N0; return N0;
// fold (sdiv X, -1) -> 0-X // fold (sdiv X, -1) -> 0-X
if (N1C && N1C->isAllOnesValue()) if (N1C && N1C->isAllOnesValue())
@ -1251,13 +1251,13 @@ SDValue DAGCombiner::visitSDIV(SDNode *N) {
} }
// fold (sdiv X, pow2) -> simple ops after legalize // fold (sdiv X, pow2) -> simple ops after legalize
if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
(isPowerOf2_64(N1C->getSignExtended()) || (isPowerOf2_64(N1C->getSExtValue()) ||
isPowerOf2_64(-N1C->getSignExtended()))) { isPowerOf2_64(-N1C->getSExtValue()))) {
// If dividing by powers of two is cheap, then don't perform the following // If dividing by powers of two is cheap, then don't perform the following
// fold. // fold.
if (TLI.isPow2DivCheap()) if (TLI.isPow2DivCheap())
return SDValue(); return SDValue();
int64_t pow2 = N1C->getSignExtended(); int64_t pow2 = N1C->getSExtValue();
int64_t abs2 = pow2 > 0 ? pow2 : -pow2; int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
unsigned lg2 = Log2_64(abs2); unsigned lg2 = Log2_64(abs2);
// Splat the sign bit into the register // Splat the sign bit into the register
@ -1283,7 +1283,7 @@ SDValue DAGCombiner::visitSDIV(SDNode *N) {
} }
// if integer divide is expensive and we satisfy the requirements, emit an // if integer divide is expensive and we satisfy the requirements, emit an
// alternate sequence. // alternate sequence.
if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) &&
!TLI.isIntDivCheap()) { !TLI.isIntDivCheap()) {
SDValue Op = BuildSDIV(N); SDValue Op = BuildSDIV(N);
if (Op.getNode()) return Op; if (Op.getNode()) return Op;

6
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -1744,13 +1744,13 @@ bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA,
if (isGAPlusOffset(N1.getNode(), GA, Offset)) { if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
if (V) { if (V) {
Offset += V->getSignExtended(); Offset += V->getSExtValue();
return true; return true;
} }
} else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
if (V) { if (V) {
Offset += V->getSignExtended(); Offset += V->getSExtValue();
return true; return true;
} }
} }
@ -2298,7 +2298,7 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
return SDValue(); // BuildSDIV only operates on i32 or i64 return SDValue(); // BuildSDIV only operates on i32 or i64
int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended(); int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSExtValue();
ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
// Multiply the numerator (operand 0) by the magic value // Multiply the numerator (operand 0) by the magic value

16
lib/Target/CellSPU/SPUISelDAGToDAG.cpp
View File

@ -41,14 +41,14 @@ namespace {
bool bool
isI64IntS10Immediate(ConstantSDNode *CN) isI64IntS10Immediate(ConstantSDNode *CN)
{ {
return isS10Constant(CN->getSignExtended()); return isS10Constant(CN->getSExtValue());
} }
//! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
bool bool
isI32IntS10Immediate(ConstantSDNode *CN) isI32IntS10Immediate(ConstantSDNode *CN)
{ {
return isS10Constant(CN->getSignExtended()); return isS10Constant(CN->getSExtValue());
} }
#if 0 #if 0
@ -65,14 +65,14 @@ namespace {
bool bool
isI32IntU10Immediate(ConstantSDNode *CN) isI32IntU10Immediate(ConstantSDNode *CN)
{ {
return isU10Constant(CN->getSignExtended()); return isU10Constant(CN->getSExtValue());
} }
//! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
bool bool
isI16IntS10Immediate(ConstantSDNode *CN) isI16IntS10Immediate(ConstantSDNode *CN)
{ {
return isS10Constant(CN->getSignExtended()); return isS10Constant(CN->getSExtValue());
} }
//! SDNode predicate for i16 sign-extended, 10-bit immediate values //! SDNode predicate for i16 sign-extended, 10-bit immediate values
@ -468,7 +468,7 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
} else if (Op1.getOpcode() == ISD::Constant } else if (Op1.getOpcode() == ISD::Constant
|| Op1.getOpcode() == ISD::TargetConstant) { || Op1.getOpcode() == ISD::TargetConstant) {
ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1); ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
int32_t offset = int32_t(CN->getSignExtended()); int32_t offset = int32_t(CN->getSExtValue());
if (Op0.getOpcode() == ISD::FrameIndex) { if (Op0.getOpcode() == ISD::FrameIndex) {
FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op0); FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op0);
@ -489,7 +489,7 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
} else if (Op0.getOpcode() == ISD::Constant } else if (Op0.getOpcode() == ISD::Constant
|| Op0.getOpcode() == ISD::TargetConstant) { || Op0.getOpcode() == ISD::TargetConstant) {
ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0); ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0);
int32_t offset = int32_t(CN->getSignExtended()); int32_t offset = int32_t(CN->getSExtValue());
if (Op1.getOpcode() == ISD::FrameIndex) { if (Op1.getOpcode() == ISD::FrameIndex) {
FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op1); FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op1);
@ -525,11 +525,11 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
if (isa<ConstantSDNode>(Op1)) { if (isa<ConstantSDNode>(Op1)) {
ConstantSDNode *CN = cast<ConstantSDNode>(Op1); ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
offset = int32_t(CN->getSignExtended()); offset = int32_t(CN->getSExtValue());
idxOp = Op0; idxOp = Op0;
} else if (isa<ConstantSDNode>(Op0)) { } else if (isa<ConstantSDNode>(Op0)) {
ConstantSDNode *CN = cast<ConstantSDNode>(Op0); ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
offset = int32_t(CN->getSignExtended()); offset = int32_t(CN->getSExtValue());
idxOp = Op1; idxOp = Op1;
} }

4
lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -1392,7 +1392,7 @@ SDValue SPU::get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
SDValue SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG, SDValue SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
MVT ValueType) { MVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) { if (ConstantSDNode *CN = getVecImm(N)) {
int64_t Value = CN->getSignExtended(); int64_t Value = CN->getSExtValue();
if (ValueType == MVT::i64) { if (ValueType == MVT::i64) {
uint64_t UValue = CN->getZExtValue(); uint64_t UValue = CN->getZExtValue();
uint32_t upper = uint32_t(UValue >> 32); uint32_t upper = uint32_t(UValue >> 32);
@ -1415,7 +1415,7 @@ SDValue SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
SDValue SPU::get_vec_i10imm(SDNode *N, SelectionDAG &DAG, SDValue SPU::get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
MVT ValueType) { MVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) { if (ConstantSDNode *CN = getVecImm(N)) {
int64_t Value = CN->getSignExtended(); int64_t Value = CN->getSExtValue();
if (ValueType == MVT::i64) { if (ValueType == MVT::i64) {
uint64_t UValue = CN->getZExtValue(); uint64_t UValue = CN->getZExtValue();
uint32_t upper = uint32_t(UValue >> 32); uint32_t upper = uint32_t(UValue >> 32);

4
lib/Target/CellSPU/SPUOperands.td
View File

@ -65,7 +65,7 @@ def HI16_vec : SDNodeXForm<scalar_to_vector, [{
// simm7 predicate - True if the immediate fits in an 7-bit signed // simm7 predicate - True if the immediate fits in an 7-bit signed
// field. // field.
def simm7: PatLeaf<(imm), [{ def simm7: PatLeaf<(imm), [{
int sextVal = int(N->getSignExtended()); int sextVal = int(N->getSExtValue());
return (sextVal >= -64 && sextVal <= 63); return (sextVal >= -64 && sextVal <= 63);
}]>; }]>;
@ -78,7 +78,7 @@ def uimm7: PatLeaf<(imm), [{
// immSExt8 predicate - True if the immediate fits in an 8-bit sign extended // immSExt8 predicate - True if the immediate fits in an 8-bit sign extended
// field. // field.
def immSExt8 : PatLeaf<(imm), [{ def immSExt8 : PatLeaf<(imm), [{
int Value = int(N->getSignExtended()); int Value = int(N->getSExtValue());
return (Value >= -(1 << 8) && Value <= (1 << 8) - 1); return (Value >= -(1 << 8) && Value <= (1 << 8) - 1);
}]>; }]>;

2
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -664,7 +664,7 @@ SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
if (LeadingOnes) { if (LeadingOnes) {
if (UniquedVals[Multiple-1].getNode() == 0) if (UniquedVals[Multiple-1].getNode() == 0)
return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended(); int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
return DAG.getTargetConstant(Val, MVT::i32); return DAG.getTargetConstant(Val, MVT::i32);
} }

6
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -775,7 +775,7 @@ bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM,
// RIP relative addressing: %rip + 32-bit displacement! // RIP relative addressing: %rip + 32-bit displacement!
if (AM.isRIPRel) { if (AM.isRIPRel) {
if (!AM.ES && AM.JT != -1 && N.getOpcode() == ISD::Constant) { if (!AM.ES && AM.JT != -1 && N.getOpcode() == ISD::Constant) {
int64_t Val = cast<ConstantSDNode>(N)->getSignExtended(); int64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
if (isInt32(AM.Disp + Val)) { if (isInt32(AM.Disp + Val)) {
AM.Disp += Val; AM.Disp += Val;
return false; return false;
@ -790,7 +790,7 @@ bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM,
switch (N.getOpcode()) { switch (N.getOpcode()) {
default: break; default: break;
case ISD::Constant: { case ISD::Constant: {
int64_t Val = cast<ConstantSDNode>(N)->getSignExtended(); int64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
if (isInt32(AM.Disp + Val)) { if (isInt32(AM.Disp + Val)) {
AM.Disp += Val; AM.Disp += Val;
return false; return false;
@ -952,7 +952,7 @@ DOUT << "AlreadySelected " << AlreadySelected << "\n";
// Address could not have picked a GV address for the displacement. // Address could not have picked a GV address for the displacement.
AM.GV == NULL && AM.GV == NULL &&
// On x86-64, the resultant disp must fit in 32-bits. // On x86-64, the resultant disp must fit in 32-bits.
isInt32(AM.Disp + CN->getSignExtended()) && isInt32(AM.Disp + CN->getSExtValue()) &&
// Check to see if the LHS & C is zero. // Check to see if the LHS & C is zero.
CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) { CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
AM.Disp += CN->getZExtValue(); AM.Disp += CN->getZExtValue();

2
lib/Target/X86/X86ISelLowering.cpp
View File

@ -5019,7 +5019,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
bool IllegalFPCMov = false; bool IllegalFPCMov = false;
if (VT.isFloatingPoint() && !VT.isVector() && if (VT.isFloatingPoint() && !VT.isVector() &&
!isScalarFPTypeInSSEReg(VT)) // FPStack? !isScalarFPTypeInSSEReg(VT)) // FPStack?
IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended()); IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
if ((Opc == X86ISD::CMP || if ((Opc == X86ISD::CMP ||
Opc == X86ISD::COMI || Opc == X86ISD::COMI ||

4
utils/TableGen/DAGISelEmitter.cpp
View File

@ -437,7 +437,7 @@ public:
if (N->isLeaf()) { if (N->isLeaf()) {
if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) { if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) {
emitCheck("cast<ConstantSDNode>(" + RootName + emitCheck("cast<ConstantSDNode>(" + RootName +
")->getSignExtended() == " + itostr(II->getValue())); ")->getSExtValue() == " + itostr(II->getValue()));
return; return;
} else if (!NodeIsComplexPattern(N)) { } else if (!NodeIsComplexPattern(N)) {
assert(0 && "Cannot match this as a leaf value!"); assert(0 && "Cannot match this as a leaf value!");
@ -726,7 +726,7 @@ public:
emitCheck("isa<ConstantSDNode>(" + RootName + ")"); emitCheck("isa<ConstantSDNode>(" + RootName + ")");
unsigned CTmp = TmpNo++; unsigned CTmp = TmpNo++;
emitCode("int64_t CN"+utostr(CTmp)+" = cast<ConstantSDNode>("+ emitCode("int64_t CN"+utostr(CTmp)+" = cast<ConstantSDNode>("+
RootName + ")->getSignExtended();"); RootName + ")->getSExtValue();");
emitCheck("CN" + utostr(CTmp) + " == " +itostr(II->getValue())); emitCheck("CN" + utostr(CTmp) + " == " +itostr(II->getValue()));
} else { } else {