mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 05:29:24 +00:00
Rename ConstantSDNode's getSignExtended to getSExtValue, for
consistancy with ConstantInt, and re-implement it in terms of ConstantInt's getSExtValue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56700 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1721,11 +1721,7 @@ public:
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const ConstantInt *getConstantIntValue() const { return Value; }
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const ConstantInt *getConstantIntValue() const { return Value; }
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const APInt &getAPIntValue() const { return Value->getValue(); }
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const APInt &getAPIntValue() const { return Value->getValue(); }
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uint64_t getZExtValue() const { return Value->getZExtValue(); }
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uint64_t getZExtValue() const { return Value->getZExtValue(); }
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int64_t getSExtValue() const { return Value->getSExtValue(); }
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int64_t getSignExtended() const {
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unsigned Bits = getValueType(0).getSizeInBits();
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return ((int64_t)getZExtValue() << (64-Bits)) >> (64-Bits);
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}
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bool isNullValue() const { return Value->isNullValue(); }
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bool isNullValue() const { return Value->isNullValue(); }
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bool isAllOnesValue() const { return Value->isAllOnesValue(); }
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bool isAllOnesValue() const { return Value->isAllOnesValue(); }
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@ -1170,12 +1170,12 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
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DAG.getConstant(N1C->getAPIntValue().logBase2(),
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DAG.getConstant(N1C->getAPIntValue().logBase2(),
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TLI.getShiftAmountTy()));
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TLI.getShiftAmountTy()));
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// fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
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// fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
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if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
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if (N1C && isPowerOf2_64(-N1C->getSExtValue())) {
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// FIXME: If the input is something that is easily negated (e.g. a
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// FIXME: If the input is something that is easily negated (e.g. a
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// single-use add), we should put the negate there.
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// single-use add), we should put the negate there.
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return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
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return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
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DAG.getNode(ISD::SHL, VT, N0,
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DAG.getNode(ISD::SHL, VT, N0,
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DAG.getConstant(Log2_64(-N1C->getSignExtended()),
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DAG.getConstant(Log2_64(-N1C->getSExtValue()),
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TLI.getShiftAmountTy())));
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TLI.getShiftAmountTy())));
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}
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}
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@ -1238,7 +1238,7 @@ SDValue DAGCombiner::visitSDIV(SDNode *N) {
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if (N0C && N1C && !N1C->isNullValue())
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if (N0C && N1C && !N1C->isNullValue())
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return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
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return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
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// fold (sdiv X, 1) -> X
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// fold (sdiv X, 1) -> X
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if (N1C && N1C->getSignExtended() == 1LL)
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if (N1C && N1C->getSExtValue() == 1LL)
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return N0;
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return N0;
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// fold (sdiv X, -1) -> 0-X
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// fold (sdiv X, -1) -> 0-X
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if (N1C && N1C->isAllOnesValue())
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if (N1C && N1C->isAllOnesValue())
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@ -1251,13 +1251,13 @@ SDValue DAGCombiner::visitSDIV(SDNode *N) {
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}
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}
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// fold (sdiv X, pow2) -> simple ops after legalize
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// fold (sdiv X, pow2) -> simple ops after legalize
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if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
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if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
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(isPowerOf2_64(N1C->getSignExtended()) ||
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(isPowerOf2_64(N1C->getSExtValue()) ||
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isPowerOf2_64(-N1C->getSignExtended()))) {
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isPowerOf2_64(-N1C->getSExtValue()))) {
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// If dividing by powers of two is cheap, then don't perform the following
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// If dividing by powers of two is cheap, then don't perform the following
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// fold.
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// fold.
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if (TLI.isPow2DivCheap())
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if (TLI.isPow2DivCheap())
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return SDValue();
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return SDValue();
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int64_t pow2 = N1C->getSignExtended();
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int64_t pow2 = N1C->getSExtValue();
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int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
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int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
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unsigned lg2 = Log2_64(abs2);
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unsigned lg2 = Log2_64(abs2);
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// Splat the sign bit into the register
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// Splat the sign bit into the register
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@ -1283,7 +1283,7 @@ SDValue DAGCombiner::visitSDIV(SDNode *N) {
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}
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}
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// if integer divide is expensive and we satisfy the requirements, emit an
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// if integer divide is expensive and we satisfy the requirements, emit an
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// alternate sequence.
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// alternate sequence.
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if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
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if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) &&
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!TLI.isIntDivCheap()) {
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!TLI.isIntDivCheap()) {
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SDValue Op = BuildSDIV(N);
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SDValue Op = BuildSDIV(N);
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if (Op.getNode()) return Op;
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if (Op.getNode()) return Op;
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@ -1744,13 +1744,13 @@ bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA,
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if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
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if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
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ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
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ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
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if (V) {
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if (V) {
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Offset += V->getSignExtended();
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Offset += V->getSExtValue();
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return true;
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return true;
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}
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}
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} else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
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} else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
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ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
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ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
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if (V) {
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if (V) {
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Offset += V->getSignExtended();
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Offset += V->getSExtValue();
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return true;
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return true;
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}
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}
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}
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}
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@ -2298,7 +2298,7 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
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if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
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if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
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return SDValue(); // BuildSDIV only operates on i32 or i64
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return SDValue(); // BuildSDIV only operates on i32 or i64
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int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
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int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSExtValue();
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ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
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ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
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// Multiply the numerator (operand 0) by the magic value
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// Multiply the numerator (operand 0) by the magic value
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@ -41,14 +41,14 @@ namespace {
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bool
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bool
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isI64IntS10Immediate(ConstantSDNode *CN)
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isI64IntS10Immediate(ConstantSDNode *CN)
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{
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{
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return isS10Constant(CN->getSignExtended());
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return isS10Constant(CN->getSExtValue());
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}
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}
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//! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
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//! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
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bool
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bool
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isI32IntS10Immediate(ConstantSDNode *CN)
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isI32IntS10Immediate(ConstantSDNode *CN)
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{
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{
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return isS10Constant(CN->getSignExtended());
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return isS10Constant(CN->getSExtValue());
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}
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}
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#if 0
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#if 0
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@ -65,14 +65,14 @@ namespace {
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bool
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bool
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isI32IntU10Immediate(ConstantSDNode *CN)
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isI32IntU10Immediate(ConstantSDNode *CN)
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{
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{
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return isU10Constant(CN->getSignExtended());
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return isU10Constant(CN->getSExtValue());
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}
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}
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//! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
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//! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
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bool
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bool
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isI16IntS10Immediate(ConstantSDNode *CN)
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isI16IntS10Immediate(ConstantSDNode *CN)
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{
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{
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return isS10Constant(CN->getSignExtended());
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return isS10Constant(CN->getSExtValue());
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}
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}
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//! SDNode predicate for i16 sign-extended, 10-bit immediate values
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//! SDNode predicate for i16 sign-extended, 10-bit immediate values
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@ -468,7 +468,7 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
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} else if (Op1.getOpcode() == ISD::Constant
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} else if (Op1.getOpcode() == ISD::Constant
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|| Op1.getOpcode() == ISD::TargetConstant) {
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|| Op1.getOpcode() == ISD::TargetConstant) {
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
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int32_t offset = int32_t(CN->getSignExtended());
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int32_t offset = int32_t(CN->getSExtValue());
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if (Op0.getOpcode() == ISD::FrameIndex) {
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if (Op0.getOpcode() == ISD::FrameIndex) {
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FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op0);
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FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op0);
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@ -489,7 +489,7 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
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} else if (Op0.getOpcode() == ISD::Constant
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} else if (Op0.getOpcode() == ISD::Constant
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|| Op0.getOpcode() == ISD::TargetConstant) {
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|| Op0.getOpcode() == ISD::TargetConstant) {
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0);
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0);
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int32_t offset = int32_t(CN->getSignExtended());
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int32_t offset = int32_t(CN->getSExtValue());
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if (Op1.getOpcode() == ISD::FrameIndex) {
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if (Op1.getOpcode() == ISD::FrameIndex) {
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FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op1);
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FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op1);
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@ -525,11 +525,11 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
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if (isa<ConstantSDNode>(Op1)) {
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if (isa<ConstantSDNode>(Op1)) {
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ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
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ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
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offset = int32_t(CN->getSignExtended());
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offset = int32_t(CN->getSExtValue());
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idxOp = Op0;
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idxOp = Op0;
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} else if (isa<ConstantSDNode>(Op0)) {
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} else if (isa<ConstantSDNode>(Op0)) {
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ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
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ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
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offset = int32_t(CN->getSignExtended());
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offset = int32_t(CN->getSExtValue());
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idxOp = Op1;
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idxOp = Op1;
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}
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}
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@ -1392,7 +1392,7 @@ SDValue SPU::get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
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SDValue SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
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SDValue SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
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MVT ValueType) {
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MVT ValueType) {
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if (ConstantSDNode *CN = getVecImm(N)) {
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if (ConstantSDNode *CN = getVecImm(N)) {
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int64_t Value = CN->getSignExtended();
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int64_t Value = CN->getSExtValue();
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if (ValueType == MVT::i64) {
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if (ValueType == MVT::i64) {
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uint64_t UValue = CN->getZExtValue();
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uint64_t UValue = CN->getZExtValue();
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uint32_t upper = uint32_t(UValue >> 32);
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uint32_t upper = uint32_t(UValue >> 32);
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@ -1415,7 +1415,7 @@ SDValue SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
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SDValue SPU::get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
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SDValue SPU::get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
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MVT ValueType) {
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MVT ValueType) {
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if (ConstantSDNode *CN = getVecImm(N)) {
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if (ConstantSDNode *CN = getVecImm(N)) {
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int64_t Value = CN->getSignExtended();
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int64_t Value = CN->getSExtValue();
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if (ValueType == MVT::i64) {
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if (ValueType == MVT::i64) {
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uint64_t UValue = CN->getZExtValue();
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uint64_t UValue = CN->getZExtValue();
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uint32_t upper = uint32_t(UValue >> 32);
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uint32_t upper = uint32_t(UValue >> 32);
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@ -65,7 +65,7 @@ def HI16_vec : SDNodeXForm<scalar_to_vector, [{
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// simm7 predicate - True if the immediate fits in an 7-bit signed
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// simm7 predicate - True if the immediate fits in an 7-bit signed
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// field.
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// field.
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def simm7: PatLeaf<(imm), [{
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def simm7: PatLeaf<(imm), [{
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int sextVal = int(N->getSignExtended());
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int sextVal = int(N->getSExtValue());
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return (sextVal >= -64 && sextVal <= 63);
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return (sextVal >= -64 && sextVal <= 63);
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}]>;
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}]>;
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@ -78,7 +78,7 @@ def uimm7: PatLeaf<(imm), [{
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// immSExt8 predicate - True if the immediate fits in an 8-bit sign extended
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// immSExt8 predicate - True if the immediate fits in an 8-bit sign extended
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// field.
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// field.
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def immSExt8 : PatLeaf<(imm), [{
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def immSExt8 : PatLeaf<(imm), [{
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int Value = int(N->getSignExtended());
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int Value = int(N->getSExtValue());
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return (Value >= -(1 << 8) && Value <= (1 << 8) - 1);
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return (Value >= -(1 << 8) && Value <= (1 << 8) - 1);
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}]>;
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}]>;
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@ -664,7 +664,7 @@ SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
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if (LeadingOnes) {
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if (LeadingOnes) {
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if (UniquedVals[Multiple-1].getNode() == 0)
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if (UniquedVals[Multiple-1].getNode() == 0)
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return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
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return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
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int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
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int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
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if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
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if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
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return DAG.getTargetConstant(Val, MVT::i32);
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return DAG.getTargetConstant(Val, MVT::i32);
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}
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}
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@ -775,7 +775,7 @@ bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM,
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// RIP relative addressing: %rip + 32-bit displacement!
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// RIP relative addressing: %rip + 32-bit displacement!
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if (AM.isRIPRel) {
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if (AM.isRIPRel) {
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if (!AM.ES && AM.JT != -1 && N.getOpcode() == ISD::Constant) {
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if (!AM.ES && AM.JT != -1 && N.getOpcode() == ISD::Constant) {
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int64_t Val = cast<ConstantSDNode>(N)->getSignExtended();
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int64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
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if (isInt32(AM.Disp + Val)) {
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if (isInt32(AM.Disp + Val)) {
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AM.Disp += Val;
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AM.Disp += Val;
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return false;
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return false;
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@ -790,7 +790,7 @@ bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM,
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switch (N.getOpcode()) {
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switch (N.getOpcode()) {
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default: break;
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default: break;
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case ISD::Constant: {
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case ISD::Constant: {
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int64_t Val = cast<ConstantSDNode>(N)->getSignExtended();
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int64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
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if (isInt32(AM.Disp + Val)) {
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if (isInt32(AM.Disp + Val)) {
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AM.Disp += Val;
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AM.Disp += Val;
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return false;
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return false;
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@ -952,7 +952,7 @@ DOUT << "AlreadySelected " << AlreadySelected << "\n";
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// Address could not have picked a GV address for the displacement.
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// Address could not have picked a GV address for the displacement.
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AM.GV == NULL &&
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AM.GV == NULL &&
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// On x86-64, the resultant disp must fit in 32-bits.
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// On x86-64, the resultant disp must fit in 32-bits.
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isInt32(AM.Disp + CN->getSignExtended()) &&
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isInt32(AM.Disp + CN->getSExtValue()) &&
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// Check to see if the LHS & C is zero.
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// Check to see if the LHS & C is zero.
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CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
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CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
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AM.Disp += CN->getZExtValue();
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AM.Disp += CN->getZExtValue();
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@ -5019,7 +5019,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
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bool IllegalFPCMov = false;
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bool IllegalFPCMov = false;
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if (VT.isFloatingPoint() && !VT.isVector() &&
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if (VT.isFloatingPoint() && !VT.isVector() &&
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!isScalarFPTypeInSSEReg(VT)) // FPStack?
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!isScalarFPTypeInSSEReg(VT)) // FPStack?
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IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
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IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
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if ((Opc == X86ISD::CMP ||
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if ((Opc == X86ISD::CMP ||
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Opc == X86ISD::COMI ||
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Opc == X86ISD::COMI ||
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@ -437,7 +437,7 @@ public:
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if (N->isLeaf()) {
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if (N->isLeaf()) {
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if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) {
|
if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) {
|
||||||
emitCheck("cast<ConstantSDNode>(" + RootName +
|
emitCheck("cast<ConstantSDNode>(" + RootName +
|
||||||
")->getSignExtended() == " + itostr(II->getValue()));
|
")->getSExtValue() == " + itostr(II->getValue()));
|
||||||
return;
|
return;
|
||||||
} else if (!NodeIsComplexPattern(N)) {
|
} else if (!NodeIsComplexPattern(N)) {
|
||||||
assert(0 && "Cannot match this as a leaf value!");
|
assert(0 && "Cannot match this as a leaf value!");
|
||||||
@ -726,7 +726,7 @@ public:
|
|||||||
emitCheck("isa<ConstantSDNode>(" + RootName + ")");
|
emitCheck("isa<ConstantSDNode>(" + RootName + ")");
|
||||||
unsigned CTmp = TmpNo++;
|
unsigned CTmp = TmpNo++;
|
||||||
emitCode("int64_t CN"+utostr(CTmp)+" = cast<ConstantSDNode>("+
|
emitCode("int64_t CN"+utostr(CTmp)+" = cast<ConstantSDNode>("+
|
||||||
RootName + ")->getSignExtended();");
|
RootName + ")->getSExtValue();");
|
||||||
|
|
||||||
emitCheck("CN" + utostr(CTmp) + " == " +itostr(II->getValue()));
|
emitCheck("CN" + utostr(CTmp) + " == " +itostr(II->getValue()));
|
||||||
} else {
|
} else {
|
||||||
|
Loading…
Reference in New Issue
Block a user