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misched: Make ScheduleDAGInstrs use the TargetSchedule interface.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164153 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2012-09-18 18:20:00 +00:00
parent 37236515cf
commit 781ab4777f
1 changed files with 14 additions and 16 deletions
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30
lib/CodeGen/ScheduleDAGInstrs.cpp
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@ -52,6 +52,9 @@ ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
DbgValues.clear(); DbgValues.clear();
assert(!(IsPostRA && MRI.getNumVirtRegs()) && assert(!(IsPostRA && MRI.getNumVirtRegs()) &&
"Virtual registers must be removed prior to PostRA scheduling"); "Virtual registers must be removed prior to PostRA scheduling");
const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
SchedModel.init(*ST.getSchedModel(), &ST, TII);
} }
/// getUnderlyingObjectFromInt - This is the function that does the work of /// getUnderlyingObjectFromInt - This is the function that does the work of
@ -274,15 +277,13 @@ void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
// perform its own adjustments. // perform its own adjustments.
SDep dep(SU, SDep::Data, LDataLatency, *Alias); SDep dep(SU, SDep::Data, LDataLatency, *Alias);
if (!UnitLatencies) { if (!UnitLatencies) {
unsigned Latency = MachineInstr *RegUse = UseOp < 0 ? 0 : UseMI;
TII->computeOperandLatency(InstrItins, SU->getInstr(), OperIdx, dep.setLatency(
(UseOp < 0 ? 0 : UseMI), UseOp); SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
dep.setLatency(Latency); RegUse, UseOp, /*FindMin=*/false));
unsigned MinLatency = dep.setMinLatency(
TII->computeOperandLatency(InstrItins, SU->getInstr(), OperIdx, SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
(UseOp < 0 ? 0 : UseMI), UseOp, RegUse, UseOp, /*FindMin=*/true));
/*FindMin=*/true);
dep.setMinLatency(MinLatency);
ST.adjustSchedDependency(SU, UseSU, dep); ST.adjustSchedDependency(SU, UseSU, dep);
} }
@ -477,13 +478,10 @@ void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
// Adjust the dependence latency using operand def/use information, then // Adjust the dependence latency using operand def/use information, then
// allow the target to perform its own adjustments. // allow the target to perform its own adjustments.
int DefOp = Def->findRegisterDefOperandIdx(Reg); int DefOp = Def->findRegisterDefOperandIdx(Reg);
unsigned Latency = dep.setLatency(
TII->computeOperandLatency(InstrItins, Def, DefOp, MI, OperIdx); SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx, false));
dep.setLatency(Latency); dep.setMinLatency(
unsigned MinLatency = SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx, true));
TII->computeOperandLatency(InstrItins, Def, DefOp, MI, OperIdx,
/*FindMin=*/true);
dep.setMinLatency(MinLatency);
const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>(); const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
ST.adjustSchedDependency(DefSU, SU, const_cast<SDep &>(dep)); ST.adjustSchedDependency(DefSU, SU, const_cast<SDep &>(dep));