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Add some simplifications for demanded bits, this allows instcombine to turn:
define i64 @test(i64 %A, i32 %B) { %tmp12 = zext i32 %B to i64 ; <i64> [#uses=1] %tmp3 = shl i64 %tmp12, 32 ; <i64> [#uses=1] %tmp5 = add i64 %tmp3, %A ; <i64> [#uses=1] %tmp6 = and i64 %tmp5, 123 ; <i64> [#uses=1] ret i64 %tmp6 } into: define i64 @test(i64 %A, i32 %B) { %tmp6 = and i64 %A, 123 ; <i64> [#uses=1] ret i64 %tmp6 } This implements Transforms/InstCombine/add2.ll:test1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34919 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1186,6 +1186,37 @@ bool InstCombiner::SimplifyDemandedBits(Value *V, uint64_t DemandedMask,
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// Bits are known zero if they are known zero in both operands and there
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// is no input carry.
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KnownZero = KnownZero2 & ~RHSVal & ~CarryBits;
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} else {
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// If the high-bits of this ADD are not demanded, then it does not demand
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// the high bits of its LHS or RHS.
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if ((DemandedMask & VTy->getSignBit()) == 0) {
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// Right fill the mask of bits for this ADD to demand the most
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// significant bit and all those below it.
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unsigned NLZ = CountLeadingZeros_64(DemandedMask);
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uint64_t DemandedFromOps = ~0ULL >> NLZ;
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if (SimplifyDemandedBits(I->getOperand(0), DemandedFromOps,
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KnownZero2, KnownOne2, Depth+1))
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return true;
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if (SimplifyDemandedBits(I->getOperand(1), DemandedFromOps,
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KnownZero2, KnownOne2, Depth+1))
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return true;
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}
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}
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break;
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case Instruction::Sub:
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// If the high-bits of this SUB are not demanded, then it does not demand
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// the high bits of its LHS or RHS.
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if ((DemandedMask & VTy->getSignBit()) == 0) {
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// Right fill the mask of bits for this SUB to demand the most
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// significant bit and all those below it.
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unsigned NLZ = CountLeadingZeros_64(DemandedMask);
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uint64_t DemandedFromOps = ~0ULL >> NLZ;
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if (SimplifyDemandedBits(I->getOperand(0), DemandedFromOps,
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KnownZero2, KnownOne2, Depth+1))
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return true;
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if (SimplifyDemandedBits(I->getOperand(1), DemandedFromOps,
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KnownZero2, KnownOne2, Depth+1))
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return true;
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}
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break;
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case Instruction::Shl:
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