mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Add patterns for some 16-bit immediate instructions, patch contributed by
Evan Cheng. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24384 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
12cf9090a4
commit
78432feff8
@ -133,8 +133,10 @@ class I<bits<8> o, Format f, dag ops, string asm>
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: X86Inst<o, f, NoImm, ops, asm>;
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class Ii8 <bits<8> o, Format f, dag ops, string asm>
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: X86Inst<o, f, Imm8 , ops, asm>;
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class Ii16<bits<8> o, Format f, dag ops, string asm>
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: X86Inst<o, f, Imm16, ops, asm>;
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class Ii16<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
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: X86Inst<o, f, Imm16, ops, asm> {
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let Pattern = pattern;
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}
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class Ii32<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
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: X86Inst<o, f, Imm32, ops, asm> {
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let Pattern = pattern;
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@ -164,7 +166,7 @@ let isTerminator = 1 in
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let isTerminator = 1, isReturn = 1, isBarrier = 1 in
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def RET : I<0xC3, RawFrm, (ops), "ret">;
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let isTerminator = 1, isReturn = 1, isBarrier = 1 in
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def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt">;
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def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", []>;
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// All branches are RawFrm, Void, Branch, and Terminators
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let isBranch = 1, isTerminator = 1 in
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@ -292,11 +294,11 @@ def IN32rr : I<0xED, RawFrm, (ops),
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"in{l} {%dx, %eax|%EAX, %DX}">, Imp<[DX],[EAX]>;
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def IN8ri : Ii16<0xE4, RawFrm, (ops i16imm:$port),
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"in{b} {$port, %al|%AL, $port}">, Imp<[], [AL]>;
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"in{b} {$port, %al|%AL, $port}", []>, Imp<[], [AL]>;
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def IN16ri : Ii16<0xE5, RawFrm, (ops i16imm:$port),
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"in{w} {$port, %ax|%AX, $port}">, Imp<[], [AX]>, OpSize;
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"in{w} {$port, %ax|%AX, $port}", []>, Imp<[], [AX]>, OpSize;
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def IN32ri : Ii16<0xE5, RawFrm, (ops i16imm:$port),
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"in{l} {$port, %eax|%EAX, $port}">, Imp<[],[EAX]>;
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"in{l} {$port, %eax|%EAX, $port}", []>, Imp<[],[EAX]>;
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def OUT8rr : I<0xEE, RawFrm, (ops),
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"out{b} {%al, %dx|%DX, %AL}">, Imp<[DX, AL], []>;
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@ -306,11 +308,11 @@ def OUT32rr : I<0xEF, RawFrm, (ops),
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"out{l} {%eax, %dx|%DX, %EAX}">, Imp<[DX, EAX], []>;
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def OUT8ir : Ii16<0xE6, RawFrm, (ops i16imm:$port),
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"out{b} {%al, $port|$port, %AL}">, Imp<[AL], []>;
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"out{b} {%al, $port|$port, %AL}", []>, Imp<[AL], []>;
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def OUT16ir : Ii16<0xE7, RawFrm, (ops i16imm:$port),
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"out{w} {%ax, $port|$port, %AX}">, Imp<[AX], []>, OpSize;
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"out{w} {%ax, $port|$port, %AX}", []>, Imp<[AX], []>, OpSize;
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def OUT32ir : Ii16<0xE7, RawFrm, (ops i16imm:$port),
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"out{l} {%eax, $port|$port, %EAX}">, Imp<[EAX], []>;
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"out{l} {%eax, $port|$port, %EAX}", []>, Imp<[EAX], []>;
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//===----------------------------------------------------------------------===//
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// Move Instructions...
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@ -324,13 +326,14 @@ def MOV32rr : I<0x89, MRMDestReg, (ops R32:$dst, R32:$src),
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def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops R8 :$dst, i8imm :$src),
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"mov{b} {$src, $dst|$dst, $src}">;
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def MOV16ri : Ii16<0xB8, AddRegFrm, (ops R16:$dst, i16imm:$src),
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"mov{w} {$src, $dst|$dst, $src}">, OpSize;
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"mov{w} {$src, $dst|$dst, $src}", [(set R16:$dst, imm:$src)]>,
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OpSize;
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def MOV32ri : Ii32<0xB8, AddRegFrm, (ops R32:$dst, i32imm:$src),
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"mov{l} {$src, $dst|$dst, $src}", [(set R32:$dst, imm:$src)]>;
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def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src),
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"mov{b} {$src, $dst|$dst, $src}">;
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def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src),
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"mov{w} {$src, $dst|$dst, $src}">, OpSize;
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"mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
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def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src),
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"mov{l} {$src, $dst|$dst, $src}", []>;
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@ -676,7 +679,8 @@ def AND8ri : Ii8<0x80, MRM4r,
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"and{b} {$src2, $dst|$dst, $src2}">;
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def AND16ri : Ii16<0x81, MRM4r,
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(ops R16:$dst, R16:$src1, i16imm:$src2),
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"and{w} {$src2, $dst|$dst, $src2}">, OpSize;
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"and{w} {$src2, $dst|$dst, $src2}",
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[(set R16:$dst, (and R16:$src1, imm:$src2))]>, OpSize;
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def AND32ri : Ii32<0x81, MRM4r,
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(ops R32:$dst, R32:$src1, i32imm:$src2),
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"and{l} {$src2, $dst|$dst, $src2}",
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@ -703,7 +707,7 @@ let isTwoAddress = 0 in {
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"and{b} {$src, $dst|$dst, $src}">;
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def AND16mi : Ii16<0x81, MRM4m,
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(ops i16mem:$dst, i16imm:$src),
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"and{w} {$src, $dst|$dst, $src}">, OpSize;
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"and{w} {$src, $dst|$dst, $src}", []>, OpSize;
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def AND32mi : Ii32<0x81, MRM4m,
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(ops i32mem:$dst, i32imm:$src),
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"and{l} {$src, $dst|$dst, $src}", []>;
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@ -734,7 +738,8 @@ def OR32rm : I<0x0B, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2),
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def OR8ri : Ii8 <0x80, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
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"or{b} {$src2, $dst|$dst, $src2}">;
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def OR16ri : Ii16<0x81, MRM1r, (ops R16:$dst, R16:$src1, i16imm:$src2),
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"or{w} {$src2, $dst|$dst, $src2}">, OpSize;
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"or{w} {$src2, $dst|$dst, $src2}",
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[(set R16:$dst, (or R16:$src1, imm:$src2))]>, OpSize;
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def OR32ri : Ii32<0x81, MRM1r, (ops R32:$dst, R32:$src1, i32imm:$src2),
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"or{l} {$src2, $dst|$dst, $src2}",
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[(set R32:$dst, (or R32:$src1, imm:$src2))]>;
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@ -753,7 +758,7 @@ let isTwoAddress = 0 in {
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def OR8mi : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src),
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"or{b} {$src, $dst|$dst, $src}">;
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def OR16mi : Ii16<0x81, MRM1m, (ops i16mem:$dst, i16imm:$src),
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"or{w} {$src, $dst|$dst, $src}">, OpSize;
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"or{w} {$src, $dst|$dst, $src}", []>, OpSize;
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def OR32mi : Ii32<0x81, MRM1m, (ops i32mem:$dst, i32imm:$src),
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"or{l} {$src, $dst|$dst, $src}", []>;
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def OR16mi8 : Ii8<0x83, MRM1m, (ops i16mem:$dst, i8imm:$src),
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@ -790,7 +795,8 @@ def XOR8ri : Ii8<0x80, MRM6r,
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"xor{b} {$src2, $dst|$dst, $src2}">;
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def XOR16ri : Ii16<0x81, MRM6r,
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(ops R16:$dst, R16:$src1, i16imm:$src2),
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"xor{w} {$src2, $dst|$dst, $src2}">, OpSize;
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"xor{w} {$src2, $dst|$dst, $src2}",
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[(set R16:$dst, (xor R16:$src1, imm:$src2))]>, OpSize;
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def XOR32ri : Ii32<0x81, MRM6r,
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(ops R32:$dst, R32:$src1, i32imm:$src2),
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"xor{l} {$src2, $dst|$dst, $src2}",
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@ -816,7 +822,7 @@ let isTwoAddress = 0 in {
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"xor{b} {$src, $dst|$dst, $src}">;
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def XOR16mi : Ii16<0x81, MRM6m,
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(ops i16mem:$dst, i16imm:$src),
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"xor{w} {$src, $dst|$dst, $src}">, OpSize;
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"xor{w} {$src, $dst|$dst, $src}", []>, OpSize;
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def XOR32mi : Ii32<0x81, MRM6m,
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(ops i32mem:$dst, i32imm:$src),
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"xor{l} {$src, $dst|$dst, $src}", []>;
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@ -1065,7 +1071,8 @@ def ADD8ri : Ii8<0x80, MRM0r, (ops R8:$dst, R8:$src1, i8imm:$src2),
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let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
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def ADD16ri : Ii16<0x81, MRM0r, (ops R16:$dst, R16:$src1, i16imm:$src2),
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"add{w} {$src2, $dst|$dst, $src2}">, OpSize;
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"add{w} {$src2, $dst|$dst, $src2}",
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[(set R16:$dst, (add R16:$src1, imm:$src2))]>, OpSize;
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def ADD32ri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2),
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"add{l} {$src2, $dst|$dst, $src2}",
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[(set R32:$dst, (add R32:$src1, imm:$src2))]>;
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@ -1086,7 +1093,7 @@ let isTwoAddress = 0 in {
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def ADD8mi : Ii8<0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2),
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"add{b} {$src2, $dst|$dst, $src2}">;
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def ADD16mi : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2),
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"add{w} {$src2, $dst|$dst, $src2}">, OpSize;
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"add{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
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def ADD32mi : Ii32<0x81, MRM0m, (ops i32mem:$dst, i32imm:$src2),
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"add{l} {$src2, $dst|$dst, $src2}", []>;
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def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i8imm :$src2),
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@ -1131,7 +1138,8 @@ def SUB32rm : I<0x2B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
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def SUB8ri : Ii8 <0x80, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2),
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"sub{b} {$src2, $dst|$dst, $src2}">;
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def SUB16ri : Ii16<0x81, MRM5r, (ops R16:$dst, R16:$src1, i16imm:$src2),
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"sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
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"sub{w} {$src2, $dst|$dst, $src2}",
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[(set R16:$dst, (sub R16:$src1, imm:$src2))]>, OpSize;
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def SUB32ri : Ii32<0x81, MRM5r, (ops R32:$dst, R32:$src1, i32imm:$src2),
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"sub{l} {$src2, $dst|$dst, $src2}",
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[(set R32:$dst, (sub R32:$src1, imm:$src2))]>;
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@ -1149,7 +1157,7 @@ let isTwoAddress = 0 in {
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def SUB8mi : Ii8<0x80, MRM5m, (ops i8mem :$dst, i8imm:$src2),
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"sub{b} {$src2, $dst|$dst, $src2}">;
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def SUB16mi : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2),
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"sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
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"sub{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
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def SUB32mi : Ii32<0x81, MRM5m, (ops i32mem:$dst, i32imm:$src2),
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"sub{l} {$src2, $dst|$dst, $src2}", []>;
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def SUB16mi8 : Ii8<0x83, MRM5m, (ops i16mem:$dst, i8imm :$src2),
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@ -1178,7 +1186,7 @@ let isTwoAddress = 0 in {
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def SBB8ri : Ii8<0x80, MRM3r, (ops R8:$dst, R8:$src1, i8imm:$src2),
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"sbb{b} {$src2, $dst|$dst, $src2}">;
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def SBB16ri : Ii16<0x81, MRM3r, (ops R16:$dst, R16:$src1, i16imm:$src2),
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"sbb{w} {$src2, $dst|$dst, $src2}">, OpSize;
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"sbb{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
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def SBB32rm : I<0x1B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
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"sbb{l} {$src2, $dst|$dst, $src2}">;
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@ -1206,7 +1214,8 @@ def IMUL32rm : I<0xAF, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
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// Suprisingly enough, these are not two address instructions!
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def IMUL16rri : Ii16<0x69, MRMSrcReg, // R16 = R16*I16
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(ops R16:$dst, R16:$src1, i16imm:$src2),
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"imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}">,
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"imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set R16:$dst, (mul R16:$src1, imm:$src2))]>,
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OpSize;
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def IMUL32rri : Ii32<0x69, MRMSrcReg, // R32 = R32*I32
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(ops R32:$dst, R32:$src1, i32imm:$src2),
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@ -1221,7 +1230,7 @@ def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // R32 = R32*I8
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def IMUL16rmi : Ii16<0x69, MRMSrcMem, // R16 = [mem16]*I16
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(ops R32:$dst, i16mem:$src1, i16imm:$src2),
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"imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}">, OpSize;
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"imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize;
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def IMUL32rmi : Ii32<0x69, MRMSrcMem, // R32 = [mem32]*I32
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(ops R32:$dst, i32mem:$src1, i32imm:$src2),
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"imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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@ -1261,7 +1270,7 @@ def TEST8ri : Ii8 <0xF6, MRM0r, // flags = R8 & imm8
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"test{b} {$src2, $src1|$src1, $src2}">;
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def TEST16ri : Ii16<0xF7, MRM0r, // flags = R16 & imm16
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(ops R16:$src1, i16imm:$src2),
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"test{w} {$src2, $src1|$src1, $src2}">, OpSize;
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"test{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
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def TEST32ri : Ii32<0xF7, MRM0r, // flags = R32 & imm32
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(ops R32:$src1, i32imm:$src2),
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"test{l} {$src2, $src1|$src1, $src2}", []>;
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@ -1270,7 +1279,7 @@ def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
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"test{b} {$src2, $src1|$src1, $src2}">;
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def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
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(ops i16mem:$src1, i16imm:$src2),
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"test{w} {$src2, $src1|$src1, $src2}">, OpSize;
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"test{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
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def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
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(ops i32mem:$src1, i32imm:$src2),
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"test{l} {$src2, $src1|$src1, $src2}", []>;
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@ -1371,7 +1380,7 @@ def CMP8ri : Ii8<0x80, MRM7r,
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"cmp{b} {$src2, $src1|$src1, $src2}">;
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def CMP16ri : Ii16<0x81, MRM7r,
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(ops R16:$src1, i16imm:$src2),
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"cmp{w} {$src2, $src1|$src1, $src2}">, OpSize;
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"cmp{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
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def CMP32ri : Ii32<0x81, MRM7r,
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(ops R32:$src1, i32imm:$src2),
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"cmp{l} {$src2, $src1|$src1, $src2}", []>;
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@ -1380,7 +1389,7 @@ def CMP8mi : Ii8 <0x80, MRM7m,
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"cmp{b} {$src2, $src1|$src1, $src2}">;
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def CMP16mi : Ii16<0x81, MRM7m,
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(ops i16mem:$src1, i16imm:$src2),
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"cmp{w} {$src2, $src1|$src1, $src2}">, OpSize;
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"cmp{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
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def CMP32mi : Ii32<0x81, MRM7m,
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(ops i32mem:$src1, i32imm:$src2),
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"cmp{l} {$src2, $src1|$src1, $src2}", []>;
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