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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21452 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2005-04-22 17:54:37 +00:00
parent dadc96f07a
commit 7847fcac17
16 changed files with 572 additions and 572 deletions
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133
lib/Target/Alpha/AlphaISelPattern.cpp
View File

@ -132,7 +132,7 @@ namespace {
//collected in a memory argument list that is a naturally aligned
//array of quadwords. In a standard call, this list, if present, must
//be passed at 0(SP).
//7 ... n 0(SP) ... (n-7)*8(SP)
//7 ... n 0(SP) ... (n-7)*8(SP)
// //#define FP $15
// //#define RA $26
@ -158,9 +158,9 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
//BuildMI(&BB, Alpha::IDEF, 0, Alpha::R26);
unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
Alpha::R19, Alpha::R20, Alpha::R21};
Alpha::R19, Alpha::R20, Alpha::R21};
unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
Alpha::F19, Alpha::F20, Alpha::F21};
Alpha::F19, Alpha::F20, Alpha::F21};
int count = 0;
//Def incoming registers
@ -286,14 +286,15 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
std::pair<SDOperand, SDOperand>
AlphaTargetLowering::LowerCallTo(SDOperand Chain,
const Type *RetTy, bool isVarArg,
SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG) {
const Type *RetTy, bool isVarArg,
SDOperand Callee, ArgListTy &Args,
SelectionDAG &DAG) {
int NumBytes = 0;
if (Args.size() > 6)
NumBytes = (Args.size() - 6) * 8;
Chain = DAG.getNode(ISD::ADJCALLSTACKDOWN, MVT::Other, Chain,
DAG.getConstant(NumBytes, getPointerTy()));
DAG.getConstant(NumBytes, getPointerTy()));
std::vector<SDOperand> args_to_use;
for (unsigned i = 0, e = Args.size(); i != e; ++i)
{
@ -911,11 +912,11 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
case ISD::FNEG:
if(ISD::FABS == N.getOperand(0).getOpcode())
{
Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Alpha::F31).addReg(Tmp1);
Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Alpha::F31).addReg(Tmp1);
} else {
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp1).addReg(Tmp1);
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp1).addReg(Tmp1);
}
return Result;
@ -1029,9 +1030,9 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
{
// Make sure we generate both values.
if (Result != notIn)
ExprMap[N.getValue(1)] = notIn; // Generate the token
ExprMap[N.getValue(1)] = notIn; // Generate the token
else
Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
DestType = N.getValue(0).getValueType();
@ -1449,12 +1450,12 @@ unsigned ISel::SelectExpr(SDOperand N) {
case MVT::i16:
case MVT::i32:
case MVT::i64:
BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R0).addReg(Alpha::R0);
break;
BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R0).addReg(Alpha::R0);
break;
case MVT::f32:
case MVT::f64:
BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F0).addReg(Alpha::F0);
break;
BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F0).addReg(Alpha::F0);
break;
}
return Result+N.ResNo;
}
@ -1571,7 +1572,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
bool isConst1 = false;
bool isConst2 = false;
int dir;
//Tmp1 = SelectExpr(N.getOperand(0));
if(N.getOperand(0).getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(N.getOperand(0))->getValue() <= 255)
@ -1667,9 +1668,9 @@ unsigned ISel::SelectExpr(SDOperand N) {
// Make sure we generate both values.
if (Result != notIn)
ExprMap[N.getValue(1)] = notIn; // Generate the token
ExprMap[N.getValue(1)] = notIn; // Generate the token
else
Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
SDOperand Chain = N.getOperand(0);
@ -1685,11 +1686,11 @@ unsigned ISel::SelectExpr(SDOperand N) {
case ISD::XOR:
//Match Not
if (N.getOperand(1).getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(N.getOperand(1))->getSignExtended() == -1)
cast<ConstantSDNode>(N.getOperand(1))->getSignExtended() == -1)
{
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, Alpha::ORNOT, 2, Result).addReg(Alpha::R31).addReg(Tmp1);
return Result;
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, Alpha::ORNOT, 2, Result).addReg(Alpha::R31).addReg(Tmp1);
return Result;
}
//Fall through
case ISD::AND:
@ -1717,32 +1718,32 @@ unsigned ISel::SelectExpr(SDOperand N) {
//Check operand(0) == Not
if (N.getOperand(0).getOpcode() == ISD::XOR &&
N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getSignExtended() == -1)
cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getSignExtended() == -1)
{
switch(opcode) {
case ISD::AND: Opc = Alpha::BIC; break;
case ISD::OR: Opc = Alpha::ORNOT; break;
case ISD::XOR: Opc = Alpha::EQV; break;
}
Tmp1 = SelectExpr(N.getOperand(1));
Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
return Result;
switch(opcode) {
case ISD::AND: Opc = Alpha::BIC; break;
case ISD::OR: Opc = Alpha::ORNOT; break;
case ISD::XOR: Opc = Alpha::EQV; break;
}
Tmp1 = SelectExpr(N.getOperand(1));
Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
return Result;
}
//Check operand(1) == Not
if (N.getOperand(1).getOpcode() == ISD::XOR &&
N.getOperand(1).getOperand(1).getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getSignExtended() == -1)
cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getSignExtended() == -1)
{
switch(opcode) {
case ISD::AND: Opc = Alpha::BIC; break;
case ISD::OR: Opc = Alpha::ORNOT; break;
case ISD::XOR: Opc = Alpha::EQV; break;
}
Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
return Result;
switch(opcode) {
case ISD::AND: Opc = Alpha::BIC; break;
case ISD::OR: Opc = Alpha::ORNOT; break;
case ISD::XOR: Opc = Alpha::EQV; break;
}
Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
return Result;
}
//Fall through
case ISD::SHL:
@ -1930,11 +1931,11 @@ unsigned ISel::SelectExpr(SDOperand N) {
assert (SrcType == MVT::f32 || SrcType == MVT::f64);
Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
if (SrcType == MVT::f32)
{
Tmp2 = MakeReg(MVT::f64);
BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Tmp1);
Tmp1 = Tmp2;
}
{
Tmp2 = MakeReg(MVT::f64);
BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Tmp1);
Tmp1 = Tmp2;
}
Tmp2 = MakeReg(MVT::f64);
BuildMI(BB, Alpha::CVTTQ, 1, Tmp2).addReg(Tmp1);
MoveFP2Int(Tmp2, Result, true);
@ -1957,19 +1958,19 @@ unsigned ISel::SelectExpr(SDOperand N) {
if (CC.getOpcode() == ISD::SETCC &&
!MVT::isInteger(SetCC->getOperand(0).getValueType()))
{ //FP Setcc -> Int Select
Tmp1 = MakeReg(MVT::f64);
Tmp1 = MakeReg(MVT::f64);
Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
Tmp3 = SelectExpr(N.getOperand(2)); //Use if FALSE
bool inv = SelectFPSetCC(CC, Tmp1);
BuildMI(BB, inv?Alpha::CMOVNE_FP:Alpha::CMOVEQ_FP, 2, Result)
.addReg(Tmp2).addReg(Tmp3).addReg(Tmp1);
return Result;
bool inv = SelectFPSetCC(CC, Tmp1);
BuildMI(BB, inv?Alpha::CMOVNE_FP:Alpha::CMOVEQ_FP, 2, Result)
.addReg(Tmp2).addReg(Tmp3).addReg(Tmp1);
return Result;
}
if (CC.getOpcode() == ISD::SETCC) {
//Int SetCC -> Select
//Dropping the CC is only useful if we are comparing to 0
if((SetCC->getOperand(1).getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(SetCC->getOperand(1))->getValue() == 0) ||
//Int SetCC -> Select
//Dropping the CC is only useful if we are comparing to 0
if((SetCC->getOperand(1).getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(SetCC->getOperand(1))->getValue() == 0) ||
(SetCC->getOperand(0).getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(SetCC->getOperand(0))->getValue() == 0))
{
@ -2013,12 +2014,12 @@ unsigned ISel::SelectExpr(SDOperand N) {
if (LeftConst) {
Tmp3 = SelectExpr(N.getOperand(2)); //Use if FALSE
BuildMI(BB, Opc, 2, Result).addReg(Tmp3)
.addImm(cast<ConstantSDNode>(N.getOperand(1))->getValue())
.addImm(cast<ConstantSDNode>(N.getOperand(1))->getValue())
.addReg(Tmp1);
} else if (RightConst) {
Tmp3 = SelectExpr(N.getOperand(1)); //Use if FALSE
BuildMI(BB, Opc, 2, Result).addReg(Tmp3)
.addImm(cast<ConstantSDNode>(N.getOperand(2))->getValue())
.addImm(cast<ConstantSDNode>(N.getOperand(2))->getValue())
.addReg(Tmp1);
} else {
Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
@ -2027,7 +2028,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
}
return Result;
}
//Otherwise, fall though
//Otherwise, fall though
}
Tmp1 = SelectExpr(N.getOperand(0)); //Cond
Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
@ -2041,13 +2042,13 @@ unsigned ISel::SelectExpr(SDOperand N) {
{
int64_t val = (int64_t)cast<ConstantSDNode>(N)->getValue();
if (val <= IMM_HIGH && val >= IMM_LOW) {
BuildMI(BB, Alpha::LDA, 2, Result).addImm(val).addReg(Alpha::R31);
BuildMI(BB, Alpha::LDA, 2, Result).addImm(val).addReg(Alpha::R31);
}
else if (val <= (int64_t)IMM_HIGH + (int64_t)IMM_HIGH * (int64_t)IMM_MULT &&
val >= (int64_t)IMM_LOW + (int64_t)IMM_LOW * (int64_t)IMM_MULT) {
Tmp1 = MakeReg(MVT::i64);
BuildMI(BB, Alpha::LDAH, 2, Tmp1).addImm(getUpper16(val)).addReg(Alpha::R31);
BuildMI(BB, Alpha::LDA, 2, Result).addImm(getLower16(val)).addReg(Tmp1);
else if (val <= (int64_t)IMM_HIGH +(int64_t)IMM_HIGH* (int64_t)IMM_MULT &&
val >= (int64_t)IMM_LOW + (int64_t)IMM_LOW * (int64_t)IMM_MULT) {
Tmp1 = MakeReg(MVT::i64);
BuildMI(BB, Alpha::LDAH, 2, Tmp1).addImm(getUpper16(val)).addReg(Alpha::R31);
BuildMI(BB, Alpha::LDA, 2, Result).addImm(getLower16(val)).addReg(Tmp1);
}
else {
MachineConstantPool *CP = BB->getParent()->getConstantPool();

10
lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@ -135,11 +135,11 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineInstr *New;
if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
New=BuildMI(Alpha::LDA, 2, Alpha::R30)
New=BuildMI(Alpha::LDA, 2, Alpha::R30)
.addImm(-Amount).addReg(Alpha::R30);
} else {
assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
New=BuildMI(Alpha::LDA, 2, Alpha::R30)
assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
New=BuildMI(Alpha::LDA, 2, Alpha::R30)
.addImm(Amount).addReg(Alpha::R30);
}
@ -272,8 +272,8 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
const MachineFrameInfo *MFI = MF.getFrameInfo();
MachineBasicBlock::iterator MBBI = prior(MBB.end());
MachineInstr *MI;
assert((MBBI->getOpcode() == Alpha::RET || MBBI->getOpcode() == Alpha::RETURN) &&
"Can only insert epilog into returning blocks");
assert((MBBI->getOpcode() == Alpha::RET || MBBI->getOpcode() == Alpha::RETURN)
&& "Can only insert epilog into returning blocks");
bool FP = hasFP(MF);

32
lib/Target/IA64/IA64AsmPrinter.cpp
View File

@ -113,14 +113,14 @@ bool IA64SharedAsmPrinter::doFinalization(Module &M) {
I->hasWeakLinkage() /* FIXME: Verify correct */)) {
SwitchSection(O, CurSection, ".data");
if (I->hasInternalLinkage()) {
O << "\t.lcomm " << name << "," << TD.getTypeSize(C->getType())
<< "," << (1 << Align);
O << "\t\t// ";
} else {
O << "\t.common " << name << "," << TD.getTypeSize(C->getType())
<< "," << (1 << Align);
O << "\t\t// ";
}
O << "\t.lcomm " << name << "," << TD.getTypeSize(C->getType())
<< "," << (1 << Align);
O << "\t\t// ";
} else {
O << "\t.common " << name << "," << TD.getTypeSize(C->getType())
<< "," << (1 << Align);
O << "\t\t// ";
}
WriteAsOperand(O, I, true, true, &M);
O << "\n";
} else {
@ -131,7 +131,7 @@ bool IA64SharedAsmPrinter::doFinalization(Module &M) {
O << "\t.weak " << name << "\n";
SwitchSection(O, CurSection, "");
O << "\t.section\t.llvm.linkonce.d." << name
<< ", \"aw\", \"progbits\"\n";
<< ", \"aw\", \"progbits\"\n";
break;
case GlobalValue::AppendingLinkage:
// FIXME: appending linkage variables should go into a section of
@ -352,19 +352,19 @@ void IA64AsmPrinter::printOp(const MachineOperand &MO,
bool Needfptr=false; // if we're computing an address @ltoff(X), do
// we need to decorate it so it becomes
// @ltoff(@fptr(X)) ?
if(F && !isBRCALLinsn /*&& F->isExternal()*/)
// @ltoff(@fptr(X)) ?
if (F && !isBRCALLinsn /*&& F->isExternal()*/)
Needfptr=true;
// if this is the target of a call instruction, we should define
// the function somewhere (GNU gas has no problem without this, but
// Intel ias rightly complains of an 'undefined symbol')
if(F /*&& isBRCALLinsn*/ && F->isExternal())
if (F /*&& isBRCALLinsn*/ && F->isExternal())
ExternalFunctionNames.insert(Mang->getValueName(MO.getGlobal()));
else
if(GV->isExternal()) // e.g. stuff like 'stdin'
ExternalObjectNames.insert(Mang->getValueName(MO.getGlobal()));
if (GV->isExternal()) // e.g. stuff like 'stdin'
ExternalObjectNames.insert(Mang->getValueName(MO.getGlobal()));
if (!isBRCALLinsn)
O << "@ltoff(";
@ -406,9 +406,9 @@ bool IA64AsmPrinter::doInitialization(Module &M) {
AsmPrinter::doInitialization(M);
O << "\n.ident \"LLVM-ia64\"\n\n"
<< "\t.psr lsb\n" // should be "msb" on HP-UX, for starters
<< "\t.psr lsb\n" // should be "msb" on HP-UX, for starters
<< "\t.radix C\n"
<< "\t.psr abi64\n"; // we only support 64 bits for now
<< "\t.psr abi64\n"; // we only support 64 bits for now
return false;
}

891
lib/Target/IA64/IA64ISelPattern.cpp
View File

File diff suppressed because it is too large Load Diff

2
lib/Target/IA64/IA64InstrInfo.cpp
View File

@ -33,7 +33,7 @@ bool IA64InstrInfo::isMoveInstr(const MachineInstr& MI,
MI.getOperand(1).isRegister() && */
"invalid register-register move instruction");
if( MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() ) {
MI.getOperand(1).isRegister() ) {
// if both operands of the MOV/FMOV are registers, then
// yes, this is a move instruction
sourceReg = MI.getOperand(1).getReg();

12
lib/Target/IA64/IA64RegisterInfo.cpp
View File

@ -133,12 +133,12 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineInstr *New;
if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) {
New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
.addSImm(-Amount);
New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
.addSImm(-Amount);
} else {
assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP);
New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
.addSImm(Amount);
assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP);
New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
.addSImm(Amount);
}
// Replace the pseudo instruction with a new instruction...
@ -225,7 +225,7 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
IA64::r108, IA64::r109, IA64::r110, IA64::r111, IA64::r112, IA64::r113,
IA64::r114, IA64::r115, IA64::r116, IA64::r117, IA64::r118, IA64::r119,
IA64::r120, IA64::r121, IA64::r122, IA64::r123, IA64::r124, IA64::r125,
IA64::r126, IA64::r127 };
IA64::r126, IA64::r127 };
unsigned numStackedGPRsUsed=0;
for(int i=0; i<96; i++) {

8
lib/Target/IA64/IA64TargetMachine.cpp
View File

@ -56,10 +56,10 @@ unsigned IA64TargetMachine::getModuleMatchQuality(const Module &M) {
if (TT.size() >= 4) {
if( (TT[0]=='i' || TT[0]=='I') &&
(TT[1]=='a' || TT[1]=='A') ) {
(TT[1]=='a' || TT[1]=='A') ) {
for(unsigned int i=2; i<(TT.size()-1); i++)
if(TT[i]=='6' && TT[i+1]=='4')
seenIA64=true;
if(TT[i]=='6' && TT[i+1]=='4')
seenIA64=true;
}
if(seenIA64)
@ -80,7 +80,7 @@ IA64TargetMachine::IA64TargetMachine(const Module &M, IntrinsicLowering *IL)
// addPassesToEmitAssembly - We currently use all of the same passes as the JIT
// does to emit statically compiled machine code.
bool IA64TargetMachine::addPassesToEmitAssembly(PassManager &PM,
std::ostream &Out) {
std::ostream &Out) {
// FIXME: Implement efficient support for garbage collection intrinsics.
PM.add(createLowerGCPass());

2
lib/Target/MRegisterInfo.cpp
View File

@ -17,7 +17,7 @@ namespace llvm {
MRegisterInfo::MRegisterInfo(const MRegisterDesc *D, unsigned NR,
regclass_iterator RCB, regclass_iterator RCE,
int CFSO, int CFDO)
int CFSO, int CFDO)
: Desc(D), NumRegs(NR), RegClassBegin(RCB), RegClassEnd(RCE) {
assert(NumRegs < FirstVirtualRegister &&
"Target has too many physical registers!");

2
lib/Target/PowerPC/PPC32ISelSimple.cpp
View File

@ -1306,7 +1306,7 @@ void PPC32ISel::visitSetCondInst(SetCondInst &I) {
}
} // switch
return;
}
}
}
unsigned PPCOpcode = getPPCOpcodeForSetCCOpcode(Opcode);

7
lib/Target/PowerPC/PPC64ISelPattern.cpp
View File

@ -218,8 +218,9 @@ PPC64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
std::pair<SDOperand, SDOperand>
PPC64TargetLowering::LowerCallTo(SDOperand Chain,
const Type *RetTy, bool isVarArg,
SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG) {
const Type *RetTy, bool isVarArg,
SDOperand Callee, ArgListTy &Args,
SelectionDAG &DAG) {
// args_to_use will accumulate outgoing args for the ISD::CALL case in
// SelectExpr to use to put the arguments in the appropriate registers.
std::vector<SDOperand> args_to_use;
@ -1519,7 +1520,7 @@ void ISel::Select(SDOperand N) {
case 3:
assert(N.getOperand(1).getValueType() == MVT::i32 &&
N.getOperand(2).getValueType() == MVT::i32 &&
"Unknown two-register value!");
"Unknown two-register value!");
Select(N.getOperand(0));
Tmp1 = SelectExpr(N.getOperand(1));
Tmp2 = SelectExpr(N.getOperand(2));

2
lib/Target/PowerPC/PPC64RegisterInfo.cpp
View File

@ -50,7 +50,7 @@ PPC64RegisterInfo::PPC64RegisterInfo()
static const TargetRegisterClass *getClass(unsigned SrcReg) {
if (PPC64::FPRCRegisterClass->contains(SrcReg))
return PPC64::FPRCRegisterClass;
return PPC64::FPRCRegisterClass;
assert(PPC64::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR");
return PPC64::GPRCRegisterClass;
}

7
lib/Target/PowerPC/PPCISelPattern.cpp
View File

@ -263,8 +263,9 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
std::pair<SDOperand, SDOperand>
PPC32TargetLowering::LowerCallTo(SDOperand Chain,
const Type *RetTy, bool isVarArg,
SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG) {
const Type *RetTy, bool isVarArg,
SDOperand Callee, ArgListTy &Args,
SelectionDAG &DAG) {
// args_to_use will accumulate outgoing args for the ISD::CALL case in
// SelectExpr to use to put the arguments in the appropriate registers.
std::vector<SDOperand> args_to_use;
@ -2366,7 +2367,7 @@ void ISel::Select(SDOperand N) {
case 3:
assert(N.getOperand(1).getValueType() == MVT::i32 &&
N.getOperand(2).getValueType() == MVT::i32 &&
"Unknown two-register value!");
"Unknown two-register value!");
Select(N.getOperand(0));
Tmp1 = SelectExpr(N.getOperand(1));
Tmp2 = SelectExpr(N.getOperand(2));

2
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -50,7 +50,7 @@ PPC32RegisterInfo::PPC32RegisterInfo()
static const TargetRegisterClass *getClass(unsigned SrcReg) {
if (PPC32::FPRCRegisterClass->contains(SrcReg))
return PPC32::FPRCRegisterClass;
return PPC32::FPRCRegisterClass;
assert(PPC32::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR");
return PPC32::GPRCRegisterClass;
}

2
lib/Target/Skeleton/SkeletonTargetMachine.cpp
View File

@ -38,7 +38,7 @@ SkeletonTargetMachine::SkeletonTargetMachine(const Module &M,
/// to implement a static compiler for this target.
///
bool SkeletonTargetMachine::addPassesToEmitAssembly(PassManager &PM,
std::ostream &Out) {
std::ostream &Out) {
// <insert instruction selector passes here>
PM.add(createRegisterAllocator());
PM.add(createPrologEpilogCodeInserter());

12
lib/Target/TargetInstrInfo.cpp
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@ -26,21 +26,21 @@ namespace llvm {
}
TargetInstrInfo::TargetInstrInfo(const TargetInstrDescriptor* Desc,
unsigned numOpcodes)
unsigned numOpcodes)
: desc(Desc), NumOpcodes(numOpcodes) {
// FIXME: TargetInstrDescriptors should not be global
assert(TargetInstrDescriptors == NULL && desc != NULL
&& "TargetMachine data structure corrupt; maybe you tried to create another TargetMachine? (only one may exist in a program)");
TargetInstrDescriptors = desc; // initialize global variable
TargetInstrDescriptors = desc; // initialize global variable
}
TargetInstrInfo::~TargetInstrInfo() {
TargetInstrDescriptors = NULL; // reset global variable
TargetInstrDescriptors = NULL; // reset global variable
}
// FIXME: SPARCV9 SPECIFIC!
bool TargetInstrInfo::constantFitsInImmedField(MachineOpCode opCode,
int64_t intValue) const {
int64_t intValue) const {
// First, check if opCode has an immed field.
bool isSignExtended;
uint64_t maxImmedValue = maxImmedConstant(opCode, isSignExtended);
@ -52,8 +52,8 @@ bool TargetInstrInfo::constantFitsInImmedField(MachineOpCode opCode,
// Now check if the constant fits
if (intValue <= (int64_t) maxImmedValue &&
intValue >= -((int64_t) maxImmedValue+1))
return true;
intValue >= -((int64_t) maxImmedValue+1))
return true;
}
return false;

20
lib/Target/TargetSchedInfo.cpp
View File

@ -43,7 +43,7 @@ CPUResource* CPUResource::getCPUResource(resourceId_t id) {
//
inline static bool
RUConflict(const std::vector<resourceId_t>& fromRVec,
const std::vector<resourceId_t>& toRVec)
const std::vector<resourceId_t>& toRVec)
{
unsigned fN = fromRVec.size(), tN = toRVec.size();
@ -63,7 +63,7 @@ RUConflict(const std::vector<resourceId_t>& fromRVec,
static CycleCount_t
ComputeMinGap(const InstrRUsage &fromRU,
const InstrRUsage &toRU)
const InstrRUsage &toRU)
{
CycleCount_t minGap = 0;
@ -92,7 +92,7 @@ ComputeMinGap(const InstrRUsage &fromRU,
//---------------------------------------------------------------------------
// class TargetSchedInfo
// Interface to machine description for instruction scheduling
// Interface to machine description for instruction scheduling
//---------------------------------------------------------------------------
TargetSchedInfo::TargetSchedInfo(const TargetMachine& tgt,
@ -112,8 +112,8 @@ TargetSchedInfo::TargetSchedInfo(const TargetMachine& tgt,
void
TargetSchedInfo::initializeResources()
{
assert(MAX_NUM_SLOTS >= (int)getMaxNumIssueTotal()
&& "Insufficient slots for static data! Increase MAX_NUM_SLOTS");
assert(MAX_NUM_SLOTS >= (int)getMaxNumIssueTotal() &&
"Insufficient slots for static data! Increase MAX_NUM_SLOTS");
// First, compute common resource usage info for each class because
// most instructions will probably behave the same as their class.
@ -134,8 +134,7 @@ TargetSchedInfo::initializeResources()
void
TargetSchedInfo::computeInstrResources(const std::vector<InstrRUsage>&
instrRUForClasses)
{
instrRUForClasses) {
int numOpCodes = mii->getNumOpcodes();
instrRUsages.resize(numOpCodes);
@ -164,8 +163,7 @@ TargetSchedInfo::computeInstrResources(const std::vector<InstrRUsage>&
void
TargetSchedInfo::computeIssueGaps(const std::vector<InstrRUsage>&
instrRUForClasses)
{
instrRUForClasses) {
int numOpCodes = mii->getNumOpcodes();
issueGaps.resize(numOpCodes);
conflictLists.resize(numOpCodes);
@ -206,7 +204,7 @@ TargetSchedInfo::computeIssueGaps(const std::vector<InstrRUsage>&
void InstrRUsage::setTo(const InstrClassRUsage& classRU) {
sameAsClass = true;
sameAsClass = true;
isSingleIssue = classRU.isSingleIssue;
breaksGroup = classRU.breaksGroup;
numBubbles = classRU.numBubbles;
@ -222,7 +220,7 @@ void InstrRUsage::setTo(const InstrClassRUsage& classRU) {
for (unsigned i=0; i < classRU.numRUEntries; i++)
for (unsigned c=classRU.V[i].startCycle, NC = c + classRU.V[i].numCycles;
c < NC; c++)
c < NC; c++)
this->resourcesByCycle[c].push_back(classRU.V[i].resourceId);
// Sort each resource usage vector by resourceId_t to speed up conflict