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[mips] Add highly experimental support for MIPS-I, MIPS-II, MIPS-III, and MIPS-V

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Summary:
These processors will only be available for the integrated assembler at
first (CodeGen will emit a fatal error saying they are not implemented).

The intention is to work through the existing instructions and correctly
annotate the ISA they were added in so that we have a sufficiently good
base to start MIPS64r6 development. MIPS64r6 removes/re-encodes certain
instructions and I believe it is best to define ISA's using set-union's
as far as possible rather than using set-subtraction.

Reviewers: vmedic

Subscribers: emaste, llvm-commits

Differential Revision: http://reviews.llvm.org/D3569

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208221 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
2014-05-07 16:25:22 +00:00
parent 459a8aaee2
commit 7858e495e9
11 changed files with 46 additions and 21 deletions
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13
lib/Target/Mips/MipsSubtarget.cpp
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@@ -107,6 +107,19 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUName);
// Don't even attempt to generate code for MIPS-I, MIPS-II, MIPS-III, and
// MIPS-V. They have not been tested and currently exist for the integrated
// assembler only.
if (MipsArchVersion == Mips1)
report_fatal_error("Code generation for MIPS-I is not implemented", false);
if (MipsArchVersion == Mips2)
report_fatal_error("Code generation for MIPS-II is not implemented", false);
if (MipsArchVersion == Mips3)
report_fatal_error("Code generation for MIPS-III is not implemented",
false);
if (MipsArchVersion == Mips5)
report_fatal_error("Code generation for MIPS-V is not implemented", false);
// Assert exactly one ABI was chosen.
assert(MipsABI != UnknownABI);
assert((((getFeatureBits() & Mips::FeatureO32) != 0) +