From 7870967ba1dbba9cb185c737bc00244ce661abd4 Mon Sep 17 00:00:00 2001
From: Tim Northover <tnorthover@apple.com>
Date: Wed, 30 Apr 2014 13:37:02 +0000
Subject: [PATCH] ARM64: use 32-bit operations for uxtb & uxth

Testing will be enabled shortly with basic-a64-instructions.s

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207648 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp | 22 ++++++++++++++++---
 test/MC/ARM64/aliases.s                       |  4 ++--
 2 files changed, 21 insertions(+), 5 deletions(-)

diff --git a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
index 6a8310e8f28..ee9c61e5285 100644
--- a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
+++ b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
@@ -4196,9 +4196,8 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
       delete Op;
     }
   }
-  // FIXME: Likewise for [su]xt[bh] with a Xd dst operand
-  else if (NumOperands == 3 &&
-           (Tok == "sxtb" || Tok == "uxtb" || Tok == "sxth" || Tok == "uxth")) {
+  // FIXME: Likewise for sxt[bh] with a Xd dst operand
+  else if (NumOperands == 3 && (Tok == "sxtb" || Tok == "sxth")) {
     ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[1]);
     if (Op->isReg() &&
         ARM64MCRegisterClasses[ARM64::GPR64allRegClassID].contains(
@@ -4214,6 +4213,23 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
       }
     }
   }
+  // FIXME: Likewise for uxt[bh] with a Xd dst operand
+  else if (NumOperands == 3 && (Tok == "uxtb" || Tok == "uxth")) {
+    ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[1]);
+    if (Op->isReg() &&
+        ARM64MCRegisterClasses[ARM64::GPR64allRegClassID].contains(
+            Op->getReg())) {
+      // The source register can be Wn here, but the matcher expects a
+      // GPR32. Twiddle it here if necessary.
+      ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[1]);
+      if (Op->isReg()) {
+        unsigned Reg = getWRegFromXReg(Op->getReg());
+        Operands[1] = ARM64Operand::CreateReg(Reg, false, Op->getStartLoc(),
+                                              Op->getEndLoc(), getContext());
+        delete Op;
+      }
+    }
+  }
 
   // Yet another horrible hack to handle FMOV Rd, #0.0 using [WX]ZR.
   if (NumOperands == 3 && Tok == "fmov") {
diff --git a/test/MC/ARM64/aliases.s b/test/MC/ARM64/aliases.s
index 2bae11459a0..18c32240d2d 100644
--- a/test/MC/ARM64/aliases.s
+++ b/test/MC/ARM64/aliases.s
@@ -249,8 +249,8 @@ foo:
 ; CHECK: sxtb x1, w2
 ; CHECK: sxth x1, w2
 ; CHECK: sxtw x1, w2
-; CHECK: ubfx x1, x2, #0, #8
-; CHECK: ubfx x1, x2, #0, #16
+; CHECK: uxtb w1, w2
+; CHECK: uxth w1, w2
 ; CHECK: ubfx x1, x2, #0, #32
 
 ;-----------------------------------------------------------------------------