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Fix a crash on invalid code due to memcpy lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44378 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -779,35 +779,40 @@ void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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// to Offset to get the correct offset.
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Offset += MFI->getStackSize();
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if (isInt16(Offset)) {
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if (isIXAddr) {
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assert((Offset & 3) == 0 && "Invalid frame offset!");
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// If we can, encode the offset directly into the instruction. If this is a
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// normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
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// this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
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// clear can be encoded. This is extremely uncommon, because normally you
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// only "std" to a stack slot that is at least 4-byte aligned, but it can
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// happen in invalid code.
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if (isInt16(Offset) && (!isIXAddr || (isIXAddr & 3) == 0)) {
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if (isIXAddr)
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Offset >>= 2; // The actual encoded value has the low two bits zero.
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}
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MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
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} else {
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// Insert a set of r0 with the full offset value before the ld, st, or add
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BuildMI(MBB, II, TII.get(PPC::LIS), PPC::R0).addImm(Offset >> 16);
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BuildMI(MBB, II, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0).addImm(Offset);
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// Convert into indexed form of the instruction
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// sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
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// addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
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unsigned OperandBase;
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if (OpC != TargetInstrInfo::INLINEASM) {
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assert(ImmToIdxMap.count(OpC) &&
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"No indexed form of load or store available!");
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unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
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MI.setInstrDescriptor(TII.get(NewOpcode));
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OperandBase = 1;
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} else {
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OperandBase = OffsetOperandNo;
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}
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unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
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MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
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MI.getOperand(OperandBase+1).ChangeToRegister(PPC::R0, false);
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return;
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}
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// Insert a set of r0 with the full offset value before the ld, st, or add
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BuildMI(MBB, II, TII.get(PPC::LIS), PPC::R0).addImm(Offset >> 16);
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BuildMI(MBB, II, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0).addImm(Offset);
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// Convert into indexed form of the instruction
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// sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
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// addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
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unsigned OperandBase;
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if (OpC != TargetInstrInfo::INLINEASM) {
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assert(ImmToIdxMap.count(OpC) &&
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"No indexed form of load or store available!");
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unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
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MI.setInstrDescriptor(TII.get(NewOpcode));
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OperandBase = 1;
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} else {
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OperandBase = OffsetOperandNo;
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}
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unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
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MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
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MI.getOperand(OperandBase+1).ChangeToRegister(PPC::R0, false);
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}
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/// VRRegNo - Map from a numbered VR register to its enum value.
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19
test/CodeGen/Generic/invalid-memcpy.ll
Normal file
19
test/CodeGen/Generic/invalid-memcpy.ll
Normal file
@ -0,0 +1,19 @@
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; RUN: llvm-as < %s | llc
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; This testcase is invalid (the alignment specified for memcpy is
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; greater than the alignment guaranteed for Qux or C.0.1173), but it
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; should compile, not crash the code generator.
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@C.0.1173 = external constant [33 x i8] ; <[33 x i8]*> [#uses=1]
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define void @Bork() {
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entry:
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%Qux = alloca [33 x i8] ; <[33 x i8]*> [#uses=1]
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%Qux1 = bitcast [33 x i8]* %Qux to i8* ; <i8*> [#uses=1]
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call void @llvm.memcpy.i64( i8* %Qux1, i8* getelementptr ([33 x i8]* @C.0.1173, i32 0, i32 0), i64 33, i32 8 )
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ret void
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}
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declare void @llvm.memcpy.i64(i8*, i8*, i64, i32)
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20
test/CodeGen/PowerPC/invalid-memcpy.ll
Normal file
20
test/CodeGen/PowerPC/invalid-memcpy.ll
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@ -0,0 +1,20 @@
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; RUN: llvm-as < %s | llc -march=ppc32
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; RUN: llvm-as < %s | llc -march=ppc64
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; This testcase is invalid (the alignment specified for memcpy is
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; greater than the alignment guaranteed for Qux or C.0.1173, but it
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; should compile, not crash the code generator.
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@C.0.1173 = external constant [33 x i8] ; <[33 x i8]*> [#uses=1]
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define void @Bork() {
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entry:
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%Qux = alloca [33 x i8] ; <[33 x i8]*> [#uses=1]
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%Qux1 = bitcast [33 x i8]* %Qux to i8* ; <i8*> [#uses=1]
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call void @llvm.memcpy.i64( i8* %Qux1, i8* getelementptr ([33 x i8]* @C.0.1173, i32 0, i32 0), i64 33, i32 8 )
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ret void
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}
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declare void @llvm.memcpy.i64(i8*, i8*, i64, i32)
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